Samsung Electronics Co., Ltd. has publicly showcased its eighth-generation high-bandwidth memory, HBM5, for the first time at the Computex 2026 exhibition. This move signals the Korean chip giant is accelerating its product roadmap in the AI memory market. Against a backdrop of broadly rising memory prices, market expectations for the profitability of Korean memory manufacturers this year have been significantly revised upward.
Samsung Electronics Co., Ltd. (OTC: SSNLF)
At the event, Samsung's Chief Technology Officer Song Jae-hyuk stated that as AI systems grow more complex, competitiveness across the entire value chain—from memory and foundry to logic chips and packaging—is becoming increasingly critical. A core technical highlight of HBM5 is an innovative thermal management solution called Heat Path Block. This technology guides heat flow between semiconductor wafers, effectively mitigating heat accumulation in high-density stacked chips, thereby enhancing performance stability and operational reliability.
Regarding the HBM4E tier, Samsung had already taken the lead in late May by shipping 12-layer HBM4E samples to major global clients, becoming the first in the industry to do so. The HBM4E offers a stable pin transfer speed of 14Gbps, scalable to 16Gbps—an improvement of over 20% compared to HBM4. It provides a per-stack bandwidth of 3.6TB/s and a capacity of 48GB, representing an increase of more than 30% over the previous generation.
Significant price increases for commodity DRAM have notably strengthened the pricing power of Samsung and SK Hynix in the HBM segment, leading to substantial upward revisions in their profit forecasts. Morgan Stanley predicts Samsung's full-year operating profit for this year could surge by 464% year-on-year, with SK Hynix's profit expected to rise by approximately 280%.
Key Innovations in HBM5
The HBM5 prototype showcased by Samsung centers on the HPB thermal management technology. As computational demands for AI models continue to escalate, requiring higher memory bandwidth, the issue of heat buildup in densely stacked chips has become increasingly prominent, directly threatening chip performance and lifespan. Samsung explained that the HPB technology guides heat between semiconductor wafers, dissipating it from critical areas to improve overall operational stability.
This technology has already been validated on the HBM4E platform and is planned for commercial deployment with HBM5. Song Jae-hyuk indicated that the specific rollout schedule will depend on customer demand, leaving open the possibility of an earlier commercial launch. On the process technology front, HBM5 is planned to incorporate Samsung's sixth-generation 10-nanometer-class DRAM process and 2-nanometer logic process nodes.
Song further noted that implementing HPB technology requires redesigning and co-integrating multiple layers of chip architecture. As an integrated semiconductor manufacturer encompassing memory, foundry, and packaging, Samsung possesses a cross-segment synergy advantage that is difficult for other companies to replicate. Additionally, Samsung is preparing to become the first in the industry to deploy hybrid copper bonding advanced packaging technology, which can further enhance heat dissipation efficiency and chip performance. Samples utilizing this technology have already been provided to several customers.
Progress on HBM4E
Alongside the HBM5 outlook, Samsung also displayed wafers and chip sets from its HBM4E platform at Computex. Exhibition information revealed the product achieves a pin transfer speed of 14Gbps, with bandwidth reaching up to 4TB/s. The core memory chips utilize the 1c DRAM process, while the logic base die is manufactured by Samsung Foundry using a 4-nanometer process.
According to a Samsung announcement on May 29th, the delivered 12-layer HBM4E samples offer a 16% improvement in power efficiency and over a 14% enhancement in thermal resistance characteristics compared to the prior generation. These improvements help extend reliability and reduce energy consumption in high-load data center environments. HBM4E shares the core technology path with HBM4, aiming to improve process stability and yield. Sang Joon Hwang, Executive Vice President of Samsung's Memory Development Division, stated that HBM4E once again demonstrates Samsung's technological differentiation, and the company will continue to drive growth in the global AI memory market.
In terms of product line planning, beyond the existing 12-layer 48GB version, Samsung will subsequently launch 32GB and 64GB versions to cater to different customer needs. The mass production schedule will be aligned with customer timelines.
Favorable Market Conditions
While Samsung is actively advancing its AI memory technology, overall market price trends are providing strong support. The market view is that after the significant price increases for commodity DRAM, its profitability is now approaching HBM levels. This means Samsung and SK Hynix do not need to rely solely on HBM volume to sustain revenue, allowing them to maintain a firm stance in price negotiations.
Samsung's cautious capacity allocation strategy, which avoids over-shifting DRAM capacity to HBM production, further supports the maintenance of high price points for HBM. Reports indicate that Samsung's HBM4 negotiation prices are already around $700, representing a 20% to 30% increase over the previous HBM3E generation.
The simultaneous price increases for HBM, commodity DRAM, and NAND flash are driving comprehensive profit improvement expectations for Korean memory manufacturers. Morgan Stanley forecasts Samsung Electronics' full-year operating profit to reach approximately 245.7 trillion won, a year-on-year increase of 464%. SK Hynix's full-year operating profit is projected to be around 179.4 trillion won, up about 280% year-on-year. The earnings recovery for both companies is expected to persist throughout the year.
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