The server CPU market is undergoing a structural boom, poised to profoundly reshape the semiconductor supply chain landscape in Asia.
According to a recent research report from Bank of America Securities, the shift in AI workloads from training to inference and agentic applications is driving a sharp expansion in server CPU demand. This surge will further compete for capacity at Taiwan Semiconductor Manufacturing (TSM)'s advanced 5nm and 3nm process nodes, exacerbating the already tight supply in the foundry market.
Bank of America estimates the global total addressable market (TAM) for server CPU semiconductor manufacturing will grow from approximately $15 billion in 2025 to about $49 billion by 2028, representing a compound annual growth rate of 49%.
Concurrently, AMD and hyperscale cloud providers' ARM-based CPU solutions continue to gain market share, pushing the outsourcing penetration rate from 52% in 2025 to 71% by 2028. This opens a significant growth opportunity for Asian supply chain companies like TSM and ASE.
The report suggests the server CPU demand explosion will drive TSM's capital expenditure to $75-$80 billion by 2027, while also fueling a 52% CAGR in demand for CoWoS advanced packaging capacity, with testing and packaging firms like ASE standing as major beneficiaries.
CPU's Strategic Ascendancy: From Supporting GPU to Core AI Infrastructure
Bank of America's report notes that AI infrastructure build-out in recent years has been dominated by GPUs and custom AI accelerators, with CPUs playing a supporting role in data preprocessing, storage access management, and scheduling. However, as AI moves from training to production inference, enterprise deployment, and agentic workflows, the strategic importance of CPUs has risen significantly.
In the AI inference pipeline, the model loading phase depends on disk I/O, memory movement, and CPU speed. Scheduling, per-token control flow, memory management, and KV cache routing during the decoding phase are also highly CPU-dependent. The rapid adoption of agentic AI further amplifies this demand, as agents require planning subtasks, retrieving context, calling tools, managing state, and executing loops—operations characterized by strong sequentiality, latency sensitivity, branch intensity, and I/O intensity, making them naturally more suitable for CPU processing.
Bank of America's U.S. semiconductor analyst Vivek Arya projects the global server CPU market TAM will expand from around $35 billion in 2025 to over $170 billion by 2030, a 37% CAGR. Within this, the share of AI server CPUs is expected to rise from 52% in 2025 to over 83% by 2030, becoming the core growth driver.
Outsourcing Wave Reshapes Supply Chain: AMD and ARM Accelerate Share Gains from Intel
The server CPU manufacturing landscape is undergoing a profound transformation. The report highlights that prior to 2018, Intel dominated server CPU production through its IDM (Integrated Device Manufacturer) model, with an outsourcing TAM of only about $112 million. A turning point came in 2019 when AMD outsourced its EPYC Rome processors to TSM's 7nm process, achieving significant performance gains and subsequently eroding Intel's market share. This pushed the outsourcing manufacturing TAM to grow at an 83% CAGR to $7.7 billion by 2025.
Looking ahead, Bank of America expects AMD will continue to outperform Intel in the x86 market due to a superior process roadmap. Meanwhile, ARM-based server CPUs—whether commercial solutions like AMD Venice and Nvidia Vera, or custom solutions from hyperscale cloud providers like AWS Graviton 5, Google Axion, and Microsoft Cobalt—are set for rapid growth from a low base. The firm forecasts the server CPU outsourced production market will grow at a 65% CAGR to $34 billion by 2028.
In terms of specific products, AMD Venice server CPU supply chain production is projected to increase from 2.8 million units in 2026 to 8.7 million in 2027. Nvidia Vera CPU production is estimated at 3.6 million and 9.4 million units for 2026 and 2027, respectively. Google Axion CPU is expected to ramp up aggressively with a 2:1 CPU-to-server motherboard configuration, with production forecast at over 1.8 million units in 2026 and 5.5 million in 2027.
Pressure Mounts on TSMC's Advanced Node Supply: High Utilization for 5nm and 3nm
The server CPU demand surge will directly intensify supply pressure on TSM's advanced nodes. Bank of America estimates wafer consumption for server CPUs will rise from 16,000 wafers per month in 2025 to approximately 50,000 by 2028, accounting for 13% of TSM's wafer consumption at the 5nm node and below at that time, up from just 6% in 2025.
The bank expects revenue contribution from major customer server CPUs to TSM will rise from 1% in 2020 to 8% in 2026, and further to 12% by 2028, primarily driven by the rapid volume ramp of AMD Venice, Nvidia Vera, and hyperscale custom ARM CPUs.
Regarding capacity planning, Bank of America projects TSM's capacity for the 7nm node and below will increase from 320,000 wafers per month in 2023 to about 680,000 by 2028, a 16% CAGR. By then, advanced node capacity will constitute 40% to 45% of total capacity. The 3nm node, crucial for high-performance computing, networking, and flagship smartphone chips, is expected to maintain near-full utilization even with ongoing capacity expansion, supporting TSM's ability to continue raising prices.
Bank of America forecasts TSM's capital expenditure will reach $76 billion in 2027, climbing further to $81 billion in 2028, representing a 21% CAGR from 2026 to 2028. Despite the significant capex increase, gross margin is still expected to expand to around 68% by 2028, as depreciation growth (17% CAGR) is projected to lag revenue growth (28% CAGR).
Based on this analysis, Bank of America maintains a Buy rating on TSM, raising its target price from NT$2,560 to NT$3,060 (ADR target from $490 to $590). It also raised its 2026/2027/2028 EPS forecasts to NT$103, NT$150, and NT$177, respectively.
Surge in Advanced Packaging Demand: CoWoS Expansion Under Pressure
Server CPUs in the AI era impose higher demands on advanced packaging. Both Nvidia Vera and AMD Venice utilize CoWoS packaging, while multiple x86/ARM CPUs employ chiplet architectures. Testing cycles have also lengthened significantly due to the complexity of wafer probing, final test, burn-in, and system-level testing.
Bank of America estimates the TAM for server CPU packaging and testing will expand from about $1.9 billion in 2025 to $9.6 billion by 2028, a 71% CAGR. This would then account for 24% of the advanced backend business for TSM, ASE, and Amkor, up from 11% in 2025.
To meet the combined packaging demand from GPUs, ASICs, and server CPUs, the bank projects industry CoWoS capacity needs to expand at a 52% CAGR.
TSM is expected to lead the expansion, with its CoWoS capacity rising from 120,000 units per month in Q4 2026 to 180,000 in Q4 2027, maintaining a 63% supply share. ASE's capacity share is projected to increase from 18% in 2026 to 29% in 2027, becoming a crucial second source. Its LEAP business is forecast to grow at a 96% CAGR to around $12 billion by 2028.
In the 3D packaging domain, copper-to-copper hybrid bonding technology is emerging as the next critical node for performance enhancement.
AMD has validated this roadmap with its 3D V-Cache, and its sixth-generation EPYC Venice processor will combine TSM's SoIC-X and CoWoS-L technologies. Nvidia is expected to adopt this solution for its Feynman GPU by 2028. Google is also in early-stage discussions with the supply chain regarding custom server CPUs with multi-chip stacking. Bank of America projects TSM's SoIC capacity will increase from 20,000 units per month in Q4 2026 to 35,000 in Q4 2027, and further expand to 50,000 by Q4 2028.
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