TSMC is accelerating the expansion of its advanced packaging capacity to meet the explosive demand for AI chips.
According to reports from Taiwan on December 11, semiconductor equipment suppliers revealed that TSMC, along with non-TSMC players such as ASE Group, Amkor, and UMC, are rapidly scaling up CoWoS production. By the end of 2026, TSMC’s monthly capacity is expected to reach 127,000 wafers, while the non-TSMC alliance’s output will surge from an initial projection of 26,000 wafers to 40,000 wafers—a more than 50% increase.
In terms of customer allocation, NVIDIA continues to dominate the market, securing over half of TSMC’s CoWoS capacity with annual bookings totaling 800,000 to 850,000 wafers. Broadcom follows closely, securing more than 240,000 wafers in 2026, primarily supplying Meta and Google’s TPUs. AMD ranks third, while MediaTek has officially entered the ASIC race, booking nearly 20,000 wafers.
This expansion aligns with Morgan Stanley’s November forecast, which projected TSMC’s CoWoS monthly output to reach 120,000–130,000 wafers, a 20% increase from earlier estimates of 100,000 wafers. The move aims to match additional 3nm front-end wafer capacity to accommodate surging AI chip demand.
Notably, following NVIDIA CEO Jensen Huang’s visit to Taiwan to secure capacity for its next-generation "Rubin" platform, TSMC decided to add 20,000 monthly 3nm front-end wafers, driving a parallel boost in advanced packaging capacity.
**GPU and ASIC Demand Surge** The capacity expansion by TSMC and its rivals stems from stronger-than-expected demand from both GPU and ASIC customers.
Industry sources confirm that despite the rising prominence of Google’s TPU and speculation about ASIC players encroaching on NVIDIA’s market share, most semiconductor players believe NVIDIA, with its CUDA ecosystem, remains the leader in large-scale model training.
Huang emphasized that GPUs and ASICs serve entirely different purposes. The industry widely views ASICs as excelling in customization, low power consumption, and inference efficiency, with the two technologies developing a "symbiotic, non-competing" relationship.
Order allocations show NVIDIA will maintain its majority share even as capacity grows by 2027. Broadcom, working with Meta and Google TPU clients, emerges as the second-largest customer after NVIDIA.
Beyond NVIDIA’s established AI GPU supply chain, Google-led ASIC supply chains are gaining momentum, with AWS, xAI, and others also ramping up ASIC chip production.
The sector involves multiple major players, including SPIL, MediaTek, Global Unichip, Alchip, LandMark Optoelectronics, MPI, WinWay, Chroma, and Gold Circuit Electronics.
IC test equipment supplier Hon Hai Precision predicts ASIC customer orders will surge in the second half of 2026. MediaTek’s entry into the ASIC market, securing nearly 20,000 wafers, signals further competition expansion.
Additionally, the U.S. has approved NVIDIA’s export of its high-end H200 AI GPU to China, with Intel and AMD also expected to resume shipments, allowing the three giants to re-enter China’s AI market.
While the U.S. government will impose a 25% levy on sales, industry players consider this preferable to an outright ban. If H200 shipments proceed smoothly, NVIDIA’s 4nm and CoWoS orders could see slight upward revisions, further benefiting TSMC’s alliance.
**Next-Gen Packaging Tech Deployment Accelerates** Morgan Stanley analysts, including Tiffany Yeh, noted in a December 17 report that TSMC decided to add 20,000 monthly 3nm front-end wafers after Huang’s visit to secure capacity for the "Rubin" platform.
The bank’s AI tracker highlights that this expansion will drive a parallel surge in CoWoS capacity, projected to reach 120,000–130,000 wafers monthly by late 2026, up from earlier estimates of 100,000 wafers.
Morgan Stanley emphasized that CoWoS, as an advanced packaging technology, is critical for high-performance AI chips. As 3nm production scales, matching packaging capacity must expand to meet AI client delivery demands.
Initially, Morgan Stanley projected TSMC’s 3nm capacity at 140,000–150,000 wafers monthly by 2026, but latest updates suggest this could rise to 160,000–170,000 wafers.
If implemented, the expansion will directly impact TSMC’s capex, requiring an additional $5–7 billion, potentially pushing 2026’s total capex from $43 billion to $48–50 billion.
By 2027, TSMC will refine CoWoS technology to meet AI demand for more logic and HBM integration, mass-producing 9.5x reticle-size CoWoS to stack 12 or more HBM layers into a single package using TSMC’s advanced logic processes.
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