On October 23, well-known tech podcaster Dwarkesh Patel released a special episode. He spent two days touring Intel's fabs and research labs, speaking with five technical leaders about topics ranging from gate-all-around and backside power delivery to CFET, and even Intel's collaboration with Elon Musk's Terafab project.
These conversations point to two judgments. Chips in 2045 will continue to grow in the direction of three-dimensional stacking: transistors, interconnects, and chip-to-chip connections will all stack upward, but each new structure takes about a decade to digest heat dissipation and integration challenges. Engineers themselves have only about four years of visibility into the technology roadmap. The more immediate constraint is equipment: the host noted that AI compute has grown 3x per year for a decade, and Intel's CTO estimated that existing global equipment is roughly only enough to double advanced-process wafer output.
Intel R&D Head: 2045 Chips Will Grow Upward, Heat Is an Unavoidable Cost
Chips compute through transistors. A transistor is a micro switch whose on and off states correspond to 1 and 0. Apply voltage to its gate, and the channel beneath conducts; remove the voltage, and the channel closes.
As devices shrink, the channel cannot close tightly and current leaks through. The solution is to have the gate control the channel from more sides: planar transistors only press down from above, FinFET stands the channel up as a thin fin and wraps it on three sides, and gate-all-around cuts the channel into suspended thin ribbons, each fully wrapped by a ring.
Chris Auth, who leads Intel's current production process development, said gate-all-around was already a known endpoint back in the 1990s: "Gate-all-around really is the ultimate transistor." Earlier steps were not skipped—strained silicon, high-K metal gate, and FinFET were all done in sequence—"you don't do it before you have to."
The next step is CFET: transistors in a circuit come in N-type and P-type pairs. Today they sit side by side; CFET stacks them vertically, doubling density in the same area at the cost of more difficult inter-layer routing and harder heat dissipation.
Chris believes structures will become more aggressive by 2045. "Right now you're facing a transistor floating in interconnects, and you think: why not transistors, interconnects, more transistors, more interconnects?" Memory chips already do this—NAND flash has 3D structures—and he believes DRAM will eventually reach this point too.
Heat dissipation is the biggest limit. He categorizes the factors limiting compute into three things: how fast switches operate, how much power switches consume, and how heat is removed. Three-dimensional devices make the heat problem more prominent: "This will be a limitation, and it will always be a limitation, but these are problems we can solve." As for when it lands, he is very conservative: "Our visibility into technology scaling is about four years. Beyond those four years, you feel you can do another four. But if you talk about ten years, it's hard to say what it will look like."
Above the transistors, more than a dozen layers of metal wiring must be stacked to connect them into circuits. This layer is called the interconnect, currently using copper. Jack Kavalieros and others in the research lab are exploring replacing it with ruthenium: copper wires need a liner to adhere properly, and the thinner the wire, the larger the proportion of the cross-section the liner occupies. Ruthenium can be directly etched without a liner. They said: "At those very fine dimensions, if you can trade the liner's resistance for no liner, ruthenium starts to win." The crossover point is around a 20-nanometer pitch. They also cautioned that the previous node chose cobalt and now it is back to copper: "The leading option then was cobalt, now it's copper again, and in the future maybe ruthenium."
Chip-to-chip connections were explained by Tyler Osborn, director of advanced packaging technology development. The episode's narration first points out the contradiction: when chip area doubles, edge length only doubles, and data exchange between chips relies on edges. In AI computing, the speed of data movement often determines overall speed more than computation itself.
Hybrid bonding is one solution: skip solder bumps, align two chips' copper interfaces directly, press and heat them so the interfaces bond together, allowing contacts to be packed more densely. Tyler gave a set of numbers: 15 years ago, first-level interconnect pitch was 130 to 150 micrometers; today, Foveros in production achieves 25 micrometers, and the lab is already below 10 micrometers. This year at the IEEE ECTC conference, papers presented reliability data for hybrid bonding devices with 0.45-micrometer pitch. His assessment: "I see a very long runway here."
New Structures Take a Decade to Reach Production, Intel Sets Innovation Budgets
FinFET was validated in the lab in 1989 and reached production in 2011; gate-all-around was validated in 1988 and only reached production in 2022 by Samsung—this is the timeline given in the episode. In between, roughly 2,000 process steps must be tuned to stability, repeatable at volume on wafers (round silicon slices cut into chips) every week, with yield (the proportion of good chips) also meeting targets.
Intel's lesson came from 10 nanometers (a generation of manufacturing process, called a node in the industry). Chris recalled that scaling speed far exceeded historical levels at the time, and it had to be done without new tools: "This placed a great burden on the process and engineers." He believes the technology that should have been pushed back most was EUV (extreme ultraviolet lithography): "When we started defining 10 nanometers, the conclusion was that EUV wasn't ready yet." EUV uses 13.5-nanometer wavelength light to print circuit patterns onto wafers; the shorter the wavelength, the finer the lines that can be printed in one pass. The episode's narration laid out the result: 10 nanometers was originally scheduled for 2016 but only began manufacturing in 2018; TSMC put EUV into production in 2019, while Intel's first EUV process only produced products in 2023.
Intel's 14A external customer decision is underway, and customers value predictable progress. Chris summarized: "What we learned is not to do too much innovation in one node, because the more innovation, the higher the complexity." Intel therefore set up "phase gates": new technologies moving from pathfinding into development must meet all yield, defect, and performance targets, or they are pushed to the next generation.
The same pragmatism appears in the fab's conference rooms. Kevin Fischer has to make decisions at Hot Topics meetings when information is incomplete: "One thing you learn is that you never have a complete data set. If you wait for a complete data set, you've waited too long, and you're already too late." What he has to judge is "how much risk are we willing to take."
His example was "epitaxial nodules." Epitaxy grows new crystal layers on the wafer surface layer by layer; if it grows wild locally, it forms bumps that short adjacent areas and cause transistor failure. The team works "highly in parallel," trying multiple approaches simultaneously—adding cleaning steps to remove nodules and also finding the source. The highest-priority rush batch is called HotBox 1, which has priority on every tool. Kevin said: "Keep one carpool lane on the highway, everyone else move aside, only this one experiment can run." The cost is that "it drags down the whole factory," so factory people are reluctant to play that card.
In the research lab, new structures first get a "short flow" prototype: only a few key steps, and once measured accurately, they are assembled into complex devices. For example, CFET first makes a simplified version with one ribbon above and one below, "maybe not yet better than today's side-by-side nanosheets," but it can verify the wiring problems after stacking. Material elimination is equally direct—a new material may be ruled out because it "won't stick," or gases in subsequent steps may change its properties. "If we can't find a way to control it, for us it's a dead end."
Intel CTO: Compute Needs 3x, Equipment Only Supports 2x
The host mentioned that ASML delivers fewer than 100 EUV lithography machines per year, to be divided among Intel, TSMC, and SK Hynix, among others. Intel CTO Pushkar Ranade acknowledged this is a constraint while saying "EUV or ASML is not the only bottleneck"—"we're seeing severe shortages across all equipment." Once a process is set, equipment is locked in: "We can't just swap in a different piece of equipment to run the same process." His buffer approach is to keep equipment as common as possible between nodes: "From 18A to 14A, maybe 80% of equipment can be reused."
When the host asked whether global equipment is enough to increase advanced-process wafer output by 10x, he replied: "10x, no. About 2x, probably yes." The host pointed out that the AI industry has grown compute 3x per year for a decade. Pushkar said that unless the entire supply chain produces more, output cannot increase. The host summarized: "Output can increase within 12 months, but by 2030 it won't be much higher than current forecasts." Pushkar added the cycle: equipment orders "take 18 months to receive," which pushes into 2028, and then new buildings are needed, "basically toward the end of this decade."
Behind this is the cost structure of the foundry business. Pushkar said: "Once a fab is built, about 80% of the cost is fixed." The tracks and stations have already been paid for; one more passenger adds almost no cost, so every extra percentage point of utilization translates directly into revenue. He also attributes industry concentration to this: forty years ago there were twenty foundries, now only three remain.
On catching up with TSMC, he believes what needs to be added is scale: "What we need to catch up on is scale." "If you're talking about technology, I think we're already there, maybe a few percentage points behind in performance, power, or area density." Regarding the SemiAnalysis comparison cited by the host, he said: "First, I don't agree with your benchmark." His standard is being on time: a few percentage points behind is acceptable, "but you must be on time."
On capital expenditure, the host cited TSMC at about $50 billion this year and Intel at about $20 billion (TSMC has raised its 2026 capex to $60–64 billion). Pushkar considers the comparison unfair—TSMC is a foundry for almost everyone, while Intel mostly builds for itself, and as external customers increase, spending will rise.
Terafab is one example of external pressure. Pushkar relayed Musk's thinking: "Either we build Terafab, or there are no chips." The host pointed out that tools are the bottleneck and total global silicon won't increase because of it; Pushkar responded that power, water, and consumables can be expanded, "but tools cannot." He also said the cost of building a fab doubles every 4 to 5 years, and one High-NA lithography machine plus supporting equipment costs about $400 million—this curve cannot extend indefinitely. He offered a thought experiment: let people eat hamburgers and smoke cigars in a research fab and see what happens to yield. He admitted no existing manufacturer would do this: "This is a risk-averse industry."
At the end of the interview, the host suggested Intel commit to purchasing tools in large volumes, like Nvidia locking up memory. Pushkar replied: "If we had known then what we know today, we would have invested more about a year ago. Knowing what we know now, I think we would invest more." He also mentioned selling the flash memory business: "Obviously in hindsight, that wasn't the smartest timing." He believes the memory supply gap is larger than the compute gap.
Same High-NA Machine, Intel and TSMC Get Two Different Calculations
High-NA is an upgraded version of EUV, with the lens's numerical aperture increased from 0.33 to 0.55, allowing features about 1.7x smaller to be printed in a single exposure. When patterns are too dense, the machine cannot print them in one pass, so they must be split into two or three passes, each consuming machine time and adding another chance for defects. The narration did the math: one EUV machine costs about $200 million, and High-NA costs about twice as much; whether it pays back depends on how many exposures can be saved.
Chris said the two companies reached different conclusions about the same equipment because of architecture. "We use backside power delivery, which means your frontside pitch requirements are relaxed." Backside power delivery moves thick power lines to the back of the wafer, leaving only fine signal lines on the front, loosening routing space so High-NA can print directly in one pass. He believes TSMC lacks backside power delivery and must use tighter pitches that High-NA cannot handle, forcing it to continue using double-patterning EUV. "It's not very helpful for them, but it's very helpful for us." However, this is Intel's side of the story.
The market is currently focused on cost. TSMC Chairman C.C. Wei said at the shareholders' meeting in June that the reason High-NA has not yet reached production is purely cost. In September, reports said TSMC had agreed to use High-NA in production starting in 2030. Intel keeps it as an option for 14A, and Chris said it will be discussed case by case with customers: "It has value, and it also adds complexity."
Intel now also builds chips for other companies (foundry), and must provide customers with a process design kit (PDK) that specifies what the process can build and under what rules. Chris acknowledged that Intel spent decades only making its own products and had no formal PDK process: "18A initially had no PDK," and it was added after customer feedback. 14A will be built to that standard from the start.
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