Samsung Electronics has achieved a series of significant milestones along its AI memory technology roadmap. Following its lead in mass-producing the sixth-generation High Bandwidth Memory, HBM4, the company is now reporting positive progress in the development of the seventh-generation HBM4E and the next DRAM process node. These advancements are laying a solid foundation for Samsung to reinforce its technological leadership in the upcoming round of AI memory competition.
According to industry sources, Song Jai Hyuk, Chief Technology Officer and Head of Samsung's Semiconductor R&D Institute, stated at an internal business briefing for the Device Solutions (DS) division on June 30th that the reliability test yield for HBM4E has been raised to over 70%. The industry typically considers a yield above 80% as the threshold for a "mature" and stable process. While HBM4E is still in the reliability testing phase, a yield exceeding 70% is seen as a clear indicator that the development process has officially entered a stable phase.
At the same event, Song Jai Hyuk also revealed that the next-generation 10-nanometer-class seventh-generation DRAM process (D1d) has gained a competitive edge over rivals. The company plans to complete its Production Readiness Assessment for this process by November this year. The combination of these two developments has led the market to hold a more optimistic outlook for Samsung's competitive prospects in the next-generation AI memory arena.
HBM4E Development Accelerates with Smooth Sample Evaluations
Samsung was the first to achieve mass production and shipment of HBM4 this past February. On May 29th, the company further disclosed detailed technical specifications for its 12-layer HBM4E product and began sending samples to key customers.
HBM4 is slated for integration into Nvidia's AI accelerator "Vera Rubin," scheduled for release in the second half of this year. Its successor, HBM4E, is planned for use in Nvidia's next-generation AI accelerator, "Vera Rubin Ultra," and other products set for launch next year. Industry observers note that as sample evaluations by major customers progress steadily, the development work for mass-producing HBM4E is also proceeding smoothly.
Against this backdrop, the rise in reliability test yield to over 70% holds significant meaning. Although this figure has not yet reached the industry's recognized standard for mature yield, given the product's current development stage, it is widely interpreted as a positive signal that HBM4E is rapidly converging towards meeting mass production conditions.
D1d Process Advances with November Certification Target
Regarding the development of the next-generation DRAM process, Song Jai Hyuk indicated that the D1d process has already achieved a technological lead over competitors. The development target is to obtain the Production Readiness Assessment by November of this year.
The PRA is the final internal quality evaluation procedure before product shipment. It comprehensively verifies yield, performance, and production efficiency to determine if mass production conditions are met. Once passed, the process can formally transition to a mass production system.
The strategic importance of the D1d process extends beyond DRAM itself. Samsung plans to fully adopt this process starting from the eighth-generation HBM5. Industry analysts believe that if D1d development proceeds as planned, it will create a positive ripple effect, enhancing the overall competitiveness of next-generation DRAM and subsequent products like HBM5.
Internal Tensions Surface Over R&D Compensation
Alongside the announcement of these technical advances, another issue has surfaced within Samsung's DS division. Following the business briefing, dissatisfaction reportedly grew within the R&D organization regarding the recognition of their role and the compensation structure. Some members are calling for the company to more actively acknowledge the contributions of the R&D organization.
Samsung's management and labor previously reached an agreement for the DS division to establish a "Special Business Performance Bonus" system, funded by 10.5% of the division's operating profit. However, within the DS division, there is a significant disparity in performance bonuses between the memory business and public sectors (including the research institute), as well as the non-memory business (System LSI and foundry). Calls for improving the compensation structure are reportedly growing louder.
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