Researchers from SK hynix and the University of Virginia, among others, published a comprehensive paper in the top-tier scientific journal Nature Electronics on August 20, systematically outlining the development roadmap for co-packaged optics (CPO) technology in high-performance computing and AI. This marks the first time SK hynix has publicly disclosed its AI interconnect architecture blueprint in a journal of this caliber.
The paper asserts that HBM has addressed the memory bottleneck within chips, but as AI clusters expand to thousands of GPUs, data transmission between racks has emerged as a new constraint—referred to as the "bandwidth wall." CPO is positioned as the key pathway to overcoming this barrier.
The paper's long-term vision is to extend optical interconnects further into memory interfaces. While current solutions primarily use optical links for data transfer between processors and racks, the proposed "optics-centric" architecture employs a photonic interposer to directly connect processor resource pools (XPU pools) with memory resource pools. This enables multiple AI accelerators to share high-capacity memory, surpassing the physical limitations of existing packaging.
The paper's corresponding authors are Seunghoon Hong, head of SK hynix's AI infrastructure team, and Kyusang Lee, professor of electrical and computer engineering at the University of Virginia. Collaborating institutions include the University of Illinois Urbana-Champaign (UIUC), Nanyang Technological University (NTU), the Massachusetts Institute of Technology (MIT), and Yonsei University.
In early trading today, SK hynix surged over 11% on the back of the CPO paper and share buyback plan announcements. Domestic CPO concept stocks rallied, with Taichen Optoelectronics rising over 12%, Zhongjing Electronics hitting the daily limit, and Tianzhun Technology, Shijia Photonics, Dekeli, and Lianter Technology each gaining over 6%.
The Bandwidth Wall: Stronger Compute, More Pronounced Bottlenecks
AI model training is no longer confined to a single chip or server but operates across large-scale networks of racks and pods. In this architecture, overall system performance depends not only on the efficiency of processor-to-memory connections but also heavily on the speed of data transfer between racks.
Data indicates that compute power grows roughly threefold every two years, while interconnect bandwidth increases only about 1.4 times in the same period.
This growing gap is the source of the "bandwidth wall." Traditional copper-based electrical interconnects remain cost-effective over short distances, but as transmission speeds rise and distances lengthen, signal loss and power consumption escalate sharply, requiring increasingly complex compensation circuits and introducing greater latency.
Kyusang Lee stated directly in the paper: "Even if computing chips become more powerful, if data transfer between chips cannot keep pace, overall system performance will not improve. Replacing copper interconnects, which have inherent physical limitations, with optical interconnects is the most promising path to future scalability."
CPO: Embedding Optical Engines into Processor Packaging
The core concept of CPO is to integrate optical transceivers (TRx) into the same package as processors, enabling chips to exchange data using optical signals rather than long-distance electrical signals.
Seunghoon Hong described it as: "CPO fundamentally changes how data flows within AI systems, eliminating one of the biggest obstacles to scaling compute."
Specifically, CPO compresses the distance high-speed electrical signals must travel to the shortest possible span, with the remaining path handled by optical links. This preserves the efficiency of intra-package electrical interconnects while leveraging the low-loss properties of light for high-speed transmission across chips, racks, and pods, while also offering stronger immunity to electromagnetic interference.
The paper sets clear technical targets for next-generation AI infrastructure: per-node bandwidth exceeding 100 Tb/s, energy consumption below 1 pJ/bit, and inter-chip latency under 10 nanoseconds.
The paper also maps the CPO evolution from 2D and 2.5D interposer configurations to 3D heterogeneous stacking, listing the key technical challenges that must be overcome for commercial deployment.
A Further Goal: Extending Light to Memory Interfaces
The paper's long-term vision is to extend optical interconnects further into memory interfaces—an architectural concept that goes beyond current CPO discussions.
While existing solutions use optical interconnects primarily for data transfer between processors and racks, the proposed "optics-centric" architecture connects processor resource pools and memory resource pools directly through a photonic interposer.
The practical significance of this architecture lies in enabling multiple AI accelerators to share a large-capacity memory pool, rather than each accelerator having its own dedicated memory. This not only improves memory utilization efficiency but also gives AI infrastructure more flexible scaling capabilities as model sizes continue to grow.
Kyusang Lee noted: "Extending optical interconnects to memory interfaces will break through the physical limits around compute chips, removing constraints on memory capacity and the number of electrical connections."
Hong added: "The biggest advantage is that by improving data movement efficiency, AI systems can scale more flexibly. This ultimately provides customers with a foundation for more efficient AI infrastructure operations."
From HBM Supplier to System Architecture Participant
HBM has addressed the memory bandwidth issue within AI accelerator packaging and has been SK hynix's core competitive strength in recent years. The release of the CPO roadmap signals that the company is extending its technological footprint from individual components to system-level architecture.
Hong clearly articulated this shift in an interview: "Memory companies are evolving from providing individual components to becoming partners that help enhance the competitiveness of customers' entire systems through technologies like CPO."
Kyusang Lee also emphasized that academic-industry collaboration is indispensable in this process: "Academia excels at pushing performance boundaries, while industry understands the practical requirements of large-scale deployment—including manufacturing yields, cost, thermal management, and supply chains. Combining these two perspectives is essential to creating a viable roadmap."
He also acknowledged that the path to commercialization still faces significant hurdles: "From integrating low-power photonic devices to developing coherency protocols and improving system reliability, the challenges remain substantial. The key is co-designing memory devices, controllers, photonic components, and packaging as an integrated system."
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