Advanced packaging technology connects, protects, and tests multiple small chips, ultimately integrating them into larger processors like GPUs. NVIDIA has secured most of the packaging capacity from industry leader Taiwan Semiconductor Manufacturing, which granted CNBC a rare interview. Taiwan Semiconductor Manufacturing will build its first advanced packaging facility in the United States in Arizona this year, while expanding two new plants in Taiwan. CNBC also visited another packaging giant, Intel, whose clients include Amazon and Cisco, with recent commitments from SpaceX and Tesla.
A long-underestimated step in chip manufacturing is emerging as the next bottleneck in artificial intelligence. All microchips powering AI must be packaged into hardware that interfaces with external systems. Currently, this process—known as advanced packaging—is almost entirely conducted in Asia, with severe capacity constraints. As Taiwan Semiconductor Manufacturing prepares to construct two new plants in Arizona and Elon Musk selects Intel to handle packaging for his ambitious custom chip initiative, this segment is gaining industry attention. John Verwey of Georgetown University's Center for Security and Emerging Technology noted, "If companies don’t proactively invest in capital expenditure to address the coming surge in fab output, packaging will quickly become a bottleneck." In a rare interview, Paul Rousseau, head of North American packaging solutions at Taiwan Semiconductor Manufacturing, told CNBC that demand metrics are "rising sharply." The most advanced technology currently used by Taiwan Semiconductor Manufacturing is called Chip-on-Wafer-on-Substrate (CoWoS), which Rousseau said is growing at a remarkable 80% compound annual rate. AI leader NVIDIA has booked the majority of advanced capacity from this packaging frontrunner. Intel remains competitive with the Taiwanese giant in technical capabilities. While the U.S. chipmaker has struggled to secure major external clients for its foundry business, its packaging division already serves Amazon and Cisco. This Tuesday, Musk also chose Intel to provide packaging for custom chips destined for SpaceX, xAI, and Tesla, to be produced at a planned large-scale fab (Terafab) in Texas. Intel conducts most final packaging in Vietnam, Malaysia, and China, with some advanced packaging taking place at facilities in New Mexico, Oregon, and Chandler, Arizona—which CNBC toured last November. As the AI industry demands greater chip density, performance, and energy efficiency, manufacturers are racing to develop optimal hardware for inference tasks, bringing packaging technology into the spotlight. With transistor density approaching physical limits, innovative silicon packaging has become critical. Rousseau stated, "This is essentially a natural extension of Moore’s Law into the third dimension." For decades, individual chips (dies) cut from a single wafer were packaged into systems connecting to computers, robots, vehicles, and mobile devices. Recent AI-driven complexity explosions have spurred advanced packaging techniques. Today, multiple dies—such as logic chips and high-bandwidth memory—are packaged together to form large-scale chips like GPUs. Advanced packaging interconnects these dies, enabling communication with each other and the broader system. Chip analyst Patrick Moorhead of Moore Insights & Strategy remarked, "Roughly five or six years ago, no one was doing this." He added that packaging was once an "afterthought," often assigned to junior engineers. "Now, it’s clearly as important as the die itself." A sample chip using CoWoS packaging displayed at Taiwan Semiconductor Manufacturing’s San Jose, California office on February 20, 2026.
Bottleneck Concerns NVIDIA has locked in most of Taiwan Semiconductor Manufacturing’s advanced CoWoS capacity. With orders overflowing, Taiwan Semiconductor Manufacturing has reportedly outsourced some steps to third-party specialists like ASE and Amkor, which excel in simpler processes. ASE, the world’s largest semiconductor packaging and testing service provider, expects its advanced packaging revenue to double by 2026. The company is building a large new plant in Taiwan, and its subsidiary Silicon Precision opened a packaging facility last year, attended by NVIDIA CEO Jensen Huang. In addition to constructing two packaging plants in Arizona, Taiwan Semiconductor Manufacturing is expanding two new packaging facilities in Taiwan. Currently, 100% of Taiwan Semiconductor Manufacturing’s chips are shipped to Taiwan for packaging, even those produced at its advanced fab in Phoenix, Arizona. The company has not disclosed a timeline for completing U.S.-based packaging facilities. Leading packaging researcher Jane Vardaman of TechSearch International told CNBC, "Having packaging capacity near the Arizona fab will greatly please clients." She added that this would eliminate transit time between the U.S. and Asia, shortening delivery cycles. Intel has already positioned some packaging capacity near its new advanced 18A process chip factory in Arizona. While the U.S. chipmaker has yet to secure major external foundry clients for its 18A process fab, its foundry business head Mark Gardiner told CNBC that its packaging division has served clients since 2022, including Amazon and Cisco. Weeks after the U.S. government invested $8.9 billion in Intel in 2025, NVIDIA invested $5 billion and plans to have some chips packaged by Intel. Moorhead commented, "Chip firms want to show the U.S. government they will collaborate with Intel, and packaging is the lowest-risk way to do that." When asked if Intel could use advanced packaging as a "gateway" to secure major chip manufacturing clients, Gardiner said some customers have already "opened that door." He stated, "There are many advantages to having everything in one location." Musk is expected to become an early major client for Intel’s chip manufacturing and packaging services. Intel posted on LinkedIn this Tuesday that its "ability to design, manufacture, and package ultra-high-performance chips at scale" will support Musk’s Terafab goal of producing 1 terawatt of computing power annually for AI development. Engineer Shripad Gokhale demonstrates a Xeon server chip to CNBC’s Katie Tarasov at Intel’s advanced packaging facility in Chandler, Arizona, on November 17, 2025.
From 2D to 3D Most chips, like CPUs, use two-dimensional packaging, while more complex chips such as GPUs require advanced solutions—namely 2.5D packaging, which includes Taiwan Semiconductor Manufacturing’s CoWoS. Such chips incorporate an additional high-density interconnect layer (interposer) for tighter connections, allowing high-bandwidth memory to be placed directly around the chip and effectively breaking the "memory wall." Rousseau explained, "Compute chips can’t integrate enough memory internally to operate at full capacity. With CoWoS, we efficiently place high-bandwidth memory right next to the compute core." Taiwan Semiconductor Manufacturing pioneered 2.5D packaging in 2012 and has since released multiple iterations. The company stated that NVIDIA’s Blackwell series GPUs are the first products using its latest CoWoS-L technology. It is this latest capacity that has strained the industry, as NVIDIA has reportedly reserved the majority of it. Intel’s leading packaging technology, Embedded Multi-die Interconnect Bridge (EMIB), operates similarly but uses silicon bridges instead of an interposer. Gardiner noted, "Embedding these tiny silicon pieces only where needed offers cost advantages." Major players are developing next-generation technology: 3D packaging. Intel’s approach is called Foveros Direct, while Taiwan Semiconductor Manufacturing’s is named System-on-Integrated-Chips (SoIC). Rousseau elaborated, "Instead of placing chips side by side, we stack them vertically." They "can perform as a single chip, achieving higher performance levels." He added that Taiwan Semiconductor Manufacturing’s SoIC-based products are still years away from market release. Meanwhile, memory firms like Samsung, SK Hynix, and Micron operate their own advanced packaging plants, using 3D packaging to stack dies into high-bandwidth memory. While ramping up chip production, memory and logic chip manufacturers are exploring hybrid bonding techniques that replace traditional bumps with copper pads, increasing integration density in stacked chips. Vardaman explained, "We can use pad-to-pad connections instead of bump connections, with nearly zero distance, resulting in better power efficiency. Electrical performance also improves with shorter pathways."
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