The advanced packaging capacity at Taiwan Semiconductor Manufacturing (TSM) is continuously expanding, potentially leading to a gradual easing of the AI chip supply chain bottleneck.
According to media reports citing institutional investor views, as TSM and its partners actively expand advanced packaging capacity, the CoWoS supply-demand gap is expected to narrow significantly from the current approximate 20% to around 10% by the end of 2026, with further improvement anticipated by 2027. This development has a direct impact on the AI accelerator supply chain, which relies on CoWoS packaging technology.
Concurrently, TSM is advancing the research and development layout for its next-generation packaging platform, CoPoS (Chip-on-Panel-on-Substrate). It is reported that NVIDIA's (NVDA) Feynman platform is expected to be among the first clients to adopt this technology, with mass production targeted for the 2028-2029 timeframe.
Accelerated Capacity Expansion Narrows Supply Gap
According to a report from TrendForce, TSM's average monthly CoWoS capacity could reach 120,000 to 140,000 wafers by 2026, setting a new record. Including an additional 50,000 to 60,000 wafers of monthly capacity from outsourced semiconductor assembly and test (OSAT) partners, the industry's total monthly capacity is expected to approach 200,000 wafers.
TrendForce forecasts that the severe global shortage of 2.5D packaging capacity will begin to ease starting in 2027, supported by order spillover effects and TSM's plan to expand CoWoS capacity by over 60% by that year.
As reported by Reuters, at a technology symposium held in May this year, TSM projected that its CoWoS advanced packaging capacity would achieve a compound annual growth rate exceeding 80% between 2022 and 2027, further underscoring the scale and intensity of this expansion cycle.
Next-Gen CoPoS Platform Advances, NVIDIA Poised for Early Adoption
While continuing to expand existing CoWoS capacity, TSM is also paving the way for its next-generation advanced packaging platform, CoPoS. With wafer sizes continually increasing, CoPoS is seen as a key path to break through existing technical ceilings.
TSM established a CoPoS R&D production line at its subsidiary VisEra in 2025. Material and equipment qualification is expected to be completed as early as June 2026, with pilot production targeted for mid-2027.
According to TrendForce, NVIDIA's (NVDA) Feynman platform is expected to be the first commercial customer for CoPoS technology. This platform is projected to enter full mass production between 2028 and 2029, with primary deployment locations including TSM's Chiayi facility in Taiwan and its Arizona wafer fab in the United States.
Market Implications: Key AI Supply Chain Constraint May Ease
CoWoS packaging technology is a core process for current high-end AI accelerator production. The tightness of its capacity directly affects the shipment pace and delivery cycles for downstream AI chips. The narrowing of the supply-demand gap from 20% to 10% indicates that a key bottleneck previously constraining the expansion of AI computing hardware is loosening, which should help alleviate market concerns about AI infrastructure supply.
From a longer-term perspective, the advancement of the CoPoS platform supports TSM in building a deeper technological moat in the advanced packaging field, further solidifying its central position within the AI chip supply chain.
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