The relentless rise of AI has run into a bottleneck you can actually see and touch: the chip itself.
Over the past decade, one of the key engines of AI progress has been the steady growth of computing power. Today, AI's demand for compute is climbing so fast that chipmakers face unprecedented pressure. The problem is that even when customers are willing to spend more, leading-edge chips cannot simply be produced in vast quantities overnight.
Why not? Dwarkesh Patel spent two days touring an advanced Intel fabrication plant and interviewing several technical leaders for the Dwarkesh Podcast, trying to answer a longer-range question: what will computer chips look like in 2045? What emerged was not just a handful of new technologies, but a sustained contest over transistors, chip interconnects and manufacturing capacity.
The first hurdle: making every single chip reliably
At Intel (ASX: INTC), Chris Auth is responsible for developing processes that are now entering the manufacturing stage. He explained that the 14A process has been in development for more than three years and is getting closer to being finalized. But an advanced production line does not spring into large-scale operation the moment the design is complete. A whole fab involves roughly 2,000 process steps, and each one must be finely tuned so that wafers can be produced repeatably and reliably.
Improving yield is not a one-off task either. Engineers use in-line inspection to find defects on wafers, combine that with final electrical testing to determine where the problem lies, then design experiments, adjust the process and see whether the fix actually works. It is a continuous loop of finding problems, pinpointing causes and validating solutions. Intel (ASX: INTC) once stumbled on its 10-nanometer process: originally slated for 2016, it only began manufacturing in 2018. The lesson was sobering: technical innovation matters, but how much new technology each generation introduces must be weighed against whether it can be delivered on time. Advanced manufacturing is not only about pushing limits; it is about turning breakthroughs into dependable volume production.
The second hurdle: how transistors can keep evolving
Chip performance gains have long depended on shrinking transistors. But as dimensions approach physical limits, simply scaling down is becoming harder, forcing engineers to change the transistor structure itself. Transistors have moved from planar designs to FinFET and then to gate-all-around (GAA) architectures, all with the same core goal: better control of current so devices deliver better performance and efficiency in a smaller space.
Another important technology is backside power delivery. Traditional chips must arrange both power lines and signal lines on the front side, with the two competing for limited routing space. Moving the power network to the back of the chip frees up more room for signal routing on the front. Looking further ahead, CFET attempts to stack complementary transistors vertically to further increase integration density. Stacking, however, is not simply placing two layers of devices on top of each other. Heat dissipation, vertical connections, and the etching and filling of complex structures all have to be solved. Researchers are also exploring two-dimensional materials and new materials such as ruthenium, hoping to open new possibilities for future transistors and interconnect technology. Every step forward brings new opportunities and new engineering challenges.
The third hurdle: moving data out as fast as chips can compute
As transistor density rises, the computing power inside a chip grows quickly, but the ability to move data between chips does not grow in step. This is one of the key contradictions facing advanced computing: compute keeps getting stronger, while data movement may become the bottleneck.
Tyler Osborn, who leads advanced packaging technology at Intel (ASX: INTC), described hybrid bonding. In the past, chips could be connected through an interposer or stacked using solder bumps. Hybrid bonding seeks to align and connect the copper interconnects on two chips directly, while bonding the surrounding insulating surfaces. Eliminating the relatively bulky solder bumps enables denser connections. Shorter, denser connections not only help boost data transfer between chips but may also reduce the energy required per bit transmitted. Still, bringing this technology into mass manufacturing is not easy. Chips must be aligned with precision, and defects during manufacturing must be controlled. This shows that future chip competition is no longer just about how many transistors a single chip has, but also about how multiple chips are combined and how efficiently they work together.
Yet even as technology advances, capacity may still fail to keep up with demand. Intel (ASX: INTC) chief technology officer Pushkar Ranade pointed to another reality: making advanced chips depends on a highly specialized global supply chain of equipment. Take EUV lithography equipment: supplier ASML produces fewer than 100 units a year. Those machines must also be competed for by different chipmakers and memory manufacturers. And EUV is not the only bottleneck. A mature process often relies on specific equipment, and a shortage of one type of tool cannot simply be solved by switching to another supplier's product. Equipment, cleanrooms, power, water and other production conditions all affect how fast a fab can expand. Even if equipment is ordered today, delivery may take about 18 months; if new buildings are also needed, capacity will come online even later. Existing tools can raise output through higher utilization and optimized production flows, but dramatically expanding the industry's advanced manufacturing capacity within a few years is not easy.
Ranade believes Intel (ASX: INTC) can push advanced wafer output from its existing equipment to roughly double. But a clear gap remains between that and the rapid growth in AI compute demand. Ultimately, this race tests whether technological innovation, equipment supply, capital investment and large-scale manufacturing can all move forward at the same time. From GAA to CFET, from backside power delivery to hybrid bonding, engineers are searching for new computing space. Beyond the fab, the entire industry must also build more equipment, production lines and supporting capacity. The chip of 2045 may not simply be a shrunken version of today's chip, but a new computing platform whose structure, connections and manufacturing system have all changed. Faced with AI's ever-growing demands, can humanity keep pushing past the twin boundaries of technology and manufacturing? And when computing power no longer depends on a single chip alone, how will we redefine the limits of the chip?
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