Chip giant Advanced Micro Devices announced on May 21 that it will invest over $10 billion in Taiwan's AI ecosystem. This move aims to expand strategic collaborations with supply chain partners such as ASE, SPIL, and Powertech Technology to boost advanced packaging manufacturing capacity for next-generation AI infrastructure.
As AI applications rapidly gain traction, global customers are swiftly scaling their AI infrastructure to meet growing computational demands. AMD's Chair and CEO, Dr. Lisa Su, stated that the company is combining its leadership in high-performance computing with the Taiwan ecosystem and global strategic partners to create integrated, rack-scale AI infrastructure. This will help customers accelerate the deployment of next-generation AI systems.
This investment focuses on addressing the most significant physical bottleneck in AI hardware: advanced packaging. AMD is collaborating with ASE and SPIL to develop next-generation wafer-based 2.5D bridge interconnect technology. This technology can significantly enhance interconnect bandwidth and improve power efficiency, providing robust support for the sixth-generation EPYC CPU, codenamed Venice. Furthermore, AMD and Powertech Technology have jointly validated the industry's first 2.5D panel-level EFB interconnect technology, which supports large-scale, high-bandwidth interconnects for deploying more efficient AI systems.
These technological advancements aim to ensure the timely deployment of the AMD Helios rack-scale platform in the second half of 2026. The platform will feature Instinct MI450X GPUs, sixth-generation EPYC CPUs, and the ROCm open software stack. ODM partners including Sanmina, Wiwynn, Wistron, and Inventec are assisting in building systems based on Helios, facilitating the platform's expansion from the design phase to large-scale mass production.
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