Samsung Electronics has showcased its prototype for the eighth-generation high-bandwidth memory, HBM5, for the first time at the Computex 2026 exhibition. This move signals the Korean chip giant's continued acceleration in product deployment for the AI memory market.
Amid a broad-based surge in memory prices, market expectations for the profitability of Korean memory manufacturers this year have been significantly revised upward.
Samsung Electronics Co., Ltd.
The company's Chief Technology Officer, Song Jae-hyuk, stated at the event that as AI systems become increasingly complex, competitiveness across the entire value chain—from memory and foundry services to logic chips and packaging—is becoming more critical.
The core technological highlight of HBM5 is a thermal management innovation called Heat Path Block. This technology guides heat flow between semiconductor wafers, effectively mitigating heat accumulation in high-density stacked chips, thereby enhancing performance stability and operational reliability.
Regarding the HBM4E tier, Samsung had already begun shipping samples of its 12-layer HBM4E to major global clients in late May, becoming the first manufacturer in the industry to do so. HBM4E maintains a stable pin transfer speed of 14Gbps, scalable to 16Gbps, representing an improvement of over 20% compared to HBM4. It offers per-stack bandwidth of 3.6TB/s and a capacity of 48GB, an increase of over 30% from the previous generation.
The significant price increase in general-purpose DRAM has notably strengthened the pricing power of Samsung and SK Hynix in the HBM market, leading to substantial upward revisions in their profit forecasts. Morgan Stanley predicts that Samsung's full-year operating profit for this year could surge by 464% year-over-year, while SK Hynix's could increase by approximately 280%.
Key Developments in HBM Technology
The HBM5 prototype showcased by Samsung centers on the HPB thermal management technology. As computational demands for AI models continue to rise, memory bandwidth increases, making heat accumulation in densely stacked chips a growing concern that directly threatens chip performance and lifespan. Samsung states that HPB technology guides heat between semiconductor wafers, dissipating it from critical areas to improve overall operational stability. This technology has already been validated on the HBM4E platform and is planned for commercial deployment with HBM5.
Song Jae-hyuk noted that the specific rollout timeline will depend on customer demand, leaving open the possibility of an earlier commercial launch. On the process front, HBM5 is planned to incorporate Samsung's sixth-generation 10-nanometer class DRAM process and a 2-nanometer logic process node.
He further explained that implementing HPB technology requires redesigning and synergistically integrating multiple layers of the chip architecture. As an integrated semiconductor manufacturer encompassing memory, foundry, and packaging, Samsung possesses a cross-segment collaborative advantage that is difficult for other players to replicate.
Additionally, Samsung is preparing to become the first in the industry to deploy hybrid copper bonding advanced packaging technology, which can further enhance heat dissipation efficiency and chip performance. Samples utilizing this technology have already been provided to several customers.
Progress on HBM4E
Beyond the HBM5 outlook, Samsung also displayed wafers and chip sets for its HBM4E platform at the Computex exhibition. Information from the show indicates the product achieves a pin transfer speed of 14Gbps, with bandwidth reaching up to 4TB/s. The core memory chips use the 1c DRAM process, while the logic base die is manufactured by Samsung Foundry using a 4-nanometer process.
According to a Samsung announcement on May 29th, the delivered 12-layer HBM4E sample offers a 16% improvement in power efficiency and over a 14% enhancement in thermal resistance characteristics compared to the previous generation. These improvements help extend reliability and reduce energy consumption in high-load data center environments.
HBM4E shares a core technology path with HBM4, aimed at improving process stability and yield. Sang Joon Hwang, Executive Vice President of Samsung's Memory Development Division, stated that HBM4E once again demonstrates Samsung's technological differentiation, and the company will continue to drive growth in the global AI memory market.
Regarding product line planning, in addition to the existing 12-layer 48GB version, Samsung will subsequently launch 32GB and 64GB versions to cater to different customer needs. The mass production schedule will be aligned with customer timelines.
Favorable Market Conditions
While Samsung is actively advancing its AI memory technology portfolio, the broader memory market price trend is providing strong support. The market view is that following the significant price increases in general-purpose DRAM, its profitability has approached HBM levels. This situation allows both Samsung and SK Hynix to maintain a firm stance in price negotiations without needing to rely on HBM volume for revenue support.
Samsung has adopted a prudent capacity allocation strategy, avoiding excessive shifting of DRAM capacity to HBM production. This approach further supports the maintenance of HBM's premium pricing. Reports indicate that the negotiated price for Samsung's HBM4 is already around $700, which is 20% to 30% higher than the previous generation HBM3E.
The simultaneous price increases for HBM, general-purpose DRAM, and NAND flash memory are driving comprehensive profit improvement expectations for Korean memory manufacturers. Morgan Stanley forecasts that Samsung Electronics' full-year operating profit will reach approximately 245.7 trillion won, a year-over-year increase of 464%. SK Hynix's full-year operating profit is expected to be around 179.4 trillion won, a rise of about 280%. The performance improvement for both companies is anticipated to persist throughout the year.
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