As the parameter scale of large models, inference tokens, and agentic AI grow rapidly, the storage system is becoming the core limiting factor constraining further AI expansion.
In its latest in-depth global technology report, Morgan Stanley suggests that insufficient capacity, limited bandwidth, and high costs together form the "Memory Wall." The future competition in AI infrastructure will increasingly depend on who can break through this systemic bottleneck.
The report estimates that by 2030, agentic AI will contribute between 26% and 77% of the new global DRAM demand. Cloud storage spending is projected to increase to $418 billion, with a compound annual growth rate of approximately 8% from 2026 to 2030. Concurrently, the proportion of storage within cloud providers' capital expenditures is expected to rise from 12% in 2023 to 40% by 2027, indicating a continuous increase in capital investment intensity.
The analysis indicates that the investment thesis for the AI supply chain is gradually shifting from computing chips like GPUs towards the entire memory ecosystem. Future beneficiaries will not only include traditional memory manufacturers but also multiple sub-sectors such as process technology, packaging, interconnects, materials, and processing-in-memory.
The report forecasts that the total addressable market for new memory technologies, excluding HBM, will expand from $1.2 billion in 2025 to $23 billion by 2030. If HBM is included, the overall market size could reach $276 billion by 2030.
The Shift in AI Infrastructure Focus
The report points out that the core bottleneck in the AI industry is transitioning from a "compute wall" to a "memory wall": while processor performance continues to climb, improvements in memory bandwidth and capacity are lagging severely.
Data shows that the bandwidth per channel for DDR5 is expected to increase only from 44.8 GB/s in 2024 to 51.2 GB/s in 2026, a two-year growth of about 14%. In contrast, the global monthly generation of AI inference tokens is projected to surge from approximately 10 trillion to 3,200 trillion over the same period, a growth exceeding 320 times, drastically widening the gap.
Memory cost has also become a key constraint for AI deployment. Currently, memory-related BOM costs account for as much as 73% in CPU servers, with DRAM price per GB having rebounded to near 30-year highs. This is seen not merely as a supply shortage but as a reflection of systemic challenges in architecture, interfaces, packaging, computing paradigms, and material systems.
Consequently, the development focus of the AI industry is shifting. While past competition centered on GPUs, the future ability for system scaling will be determined by the entire memory architecture. Technological innovation aimed at the "memory wall" will become the primary driver for AI infrastructure upgrades, spanning advanced process nodes, HBM, packaging, CXL, MRDIMM, processing-in-memory, and new materials.
In essence, GPUs determine how fast AI can run, while the memory system determines how far AI can go. The next wave of AI investment opportunities will therefore extend from computing chips to the entire memory supply chain.
Six Innovation Pathways Unlocking Industry Potential
To break through the "memory wall," the report outlines six key directions for future technological evolution.
The first is advanced process technology. DRAM has entered the 1γ (1c) node era, with Samsung, SK Hynix, and Micron having initiated mass production or ramping up. However, the linewidth reduction from 1β to 1γ is less than 10%, indicating that 2D DRAM is gradually approaching physical limits. For NAND, the industry has moved into the 200- to 300-layer era, with Micron producing 276-layer products, Samsung's 9th-generation V-NAND reaching 286 layers, and SK Hynix achieving mass production of 321 layers. Roadmaps point towards surpassing 1,000 layers before 2030.
The second is memory architecture innovation. New architectures under development include PLC NAND, 3D DRAM, ZAM, and zHBM. Among these, 3D DRAM aims to break density bottlenecks through vertical stacking, although mass production with a complete capacitor structure is still some time away.
The third is advanced packaging. The HBM roadmap is advancing towards HBM4 and HBM4E, with 16-layer HBM4E expected to enter mass production in 2027, offering single-stack bandwidth of 1.5 TB/s to over 2 TB/s. SanDisk's High Bandwidth Flash (HBF) connects multiple 3D NAND arrays via TSVs, offering up to 4 TB of memory capacity. While providing bandwidth close to HBM, its capacity is 8 to 16 times greater. The first samples are expected in the second half of 2026. Additionally, the wafer-on-wafer (WoW) market is forecast to grow rapidly from $1 million in 2025 to $9.8 billion by 2030, representing a compound annual growth rate of 322%.
The fourth is peripheral interconnect chips. MRDIMM integrates MRCD and MDB chips to enable dual-channel parallel access, potentially doubling the effective bandwidth of native DDR5 frequency. CXL leverages PCIe for memory expansion, breaking the capacity limits of traditional DIMMs. The report has raised its forecast for the CXL MXC chip market size in 2030 from $990 million to $2.1 billion, and for the CXL switch chip market from $664 million to $1.9 billion. Entering the DDR6 era, the number of RCD chips used in dual-socket servers is expected to increase from 24 to 96.
The fifth is processing-in-memory/computing-in-memory (PIM/CIM). Samsung's HBM-PIM (Aquabolt-XL) and SK Hynix's GDDR6-AiM have reached the commercialization stage. Experimental data shows that PIM can reduce average memory access latency by over 50%, with performance gains in some scenarios reaching up to 16 times and energy efficiency improvements exceeding 80%.
The sixth is new materials. New material systems are being accelerated for adoption to reduce power consumption, increase memory density, and improve manufacturing processes. These include Si/SiGe superlattice channels, TiO₂-based capacitor dielectrics, HZO ferroelectric materials, and molybdenum metallization, providing support for next-generation 3D DRAM and 3D NAND.
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