According to the latest high-speed interconnect market research from TrendForce, the architecture of NVIDIA's next-generation AI computing racks indicates that future GPU design will focus on higher-density chip interconnects and faster data transmission. Chip interconnection within a rack (Scale-Up) and large-scale interconnection across racks (Scale-Out) will become central topics in data center planning. Traditional electrical transmission schemes using copper cables are limited by physical constraints and cannot meet the demands of ultra-large-scale data movement, creating opportunities for optical transmission solutions. TrendForce estimates that the penetration rate of Co-Packaged Optics (CPO) in AI data center optical communication modules will grow annually and is projected to reach 35% by 2030.
Under the NVIDIA NVLink 6 transmission protocol, a single-channel 400G SerDes achieves maximum speed, with a single GPU supporting up to 3.6 TB/s of bandwidth. At such extreme high-frequency transmission rates, signal degradation in copper cable solutions worsens with increased transmission distance, restricting usable distance to within one meter. However, as chip interconnection scales up—for example, when Scale-Up connectivity expands from a single rack to multiple racks (such as NVIDIA's 576-GPU cluster composed of eight NVL72 units)—copper cable solutions will be unable to meet requirements.
Furthermore, optical transmission employs Wavelength Division Multiplexing (WDM) technology, which uses multiple wavelengths within a single optical fiber to significantly increase transmission density—an advantage unattainable with copper cables. As a result, major cloud service providers (CSPs) are collaborating with startups to develop various optical transmission solutions, preparing for future bandwidth demands and laying the groundwork for the adoption and growth of CPO technology.
Observing NVIDIA's recent strategy regarding CPO and silicon photonics, the company utilizes TSMC's COUPE 3D packaging technology to stack logic and silicon photonic chips. By incorporating 200G PAM4 micro-ring modulators (MRMs) on the silicon photonic chips, NVIDIA achieves compact size and low power consumption while enhancing the overall bandwidth density of the optical engine. NVIDIA has also recently announced investments of $2 billion each in Lumentum and Coherent, along with multi-year procurement commitments and priority supply rights for advanced lasers and optical products. This move indicates that NVIDIA is strategically stockpiling key components for Scale-Up optical interconnects and will deeply engage in the development of lasers and optical components, suggesting that future computing infrastructure will rely more heavily on optical technology.
TrendForce anticipates that optical interconnect technology based on silicon photonics and CPO will first be adopted for Scale-Out data transmission between racks in the NVIDIA Rubin generation. Plans are also in place to integrate optical interconnects into future Scale-Up architectures to achieve even higher bandwidth density. According to TrendForce estimates, CPO penetration in optical modules for AI data centers will be only about 0.5% in 2026. As silicon photonics and CPO packaging technologies mature, Scale-Up optical interconnect data transmission across racks is expected to emerge as early as the Rubin Ultra or Feynman generation. With continuous increases in data transmission bandwidth, TrendForce projects that silicon photonics-based CPO penetration in AI data centers could reach approximately 35% by 2030. Meanwhile, new forms of optical interconnects and technologies such as Optical I/O are also likely to emerge.
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