SK Hynix is developing an innovative packaging technology for next-generation high-bandwidth memory, seeking to overcome HBM4 performance bottlenecks without significantly increasing capital expenditures. According to a Tuesday ZDNet report cited by TrendForce, industry sources revealed that SK Hynix is advancing an improved packaging architecture. Core measures include increasing DRAM chip thickness and reducing the spacing between DRAM layers, with the technology currently in the verification phase. If successfully commercialized, this approach could help SK Hynix meet the top-tier performance targets set by NVIDIA for the sixth-generation HBM4 and lay the groundwork for performance improvements in subsequent products. For the market, the potential significance of this technology lies in its low capital investment attribute. If mass production is achieved, SK Hynix could further solidify its technological leadership in the HBM competitive landscape while providing more competitive memory solutions for downstream clients like NVIDIA. However, the report also notes that scaling this technology to mass production may still face challenges.
Increasing DRAM thickness enhances stability, while reducing interlayer spacing improves power efficiency and data transfer rates. The core constraint for HBM4 performance improvement stems from its I/O count doubling to 2048 compared to the previous generation. The report states that the denser I/O layout significantly boosts bandwidth but also substantially increases the risk of signal interference. Simultaneously, efficiently transmitting voltage from the bottom logic die to the top DRAM layers presents a technical challenge in power delivery. These two challenges point to the need for optimized packaging architecture, which is the starting point for SK Hynix's current technological exploration.
The first core measure in SK Hynix's new approach is moderately increasing the thickness of the upper DRAM chips. Traditional processes typically thin DRAM via backside grinding to meet HBM4's overall height requirement of 775 micrometers. However, excessive thinning can degrade performance and make chips more sensitive to external shock. By increasing DRAM thickness, SK Hynix aims to enhance the overall structural stability of HBM4, thereby reducing the risk of yield loss caused by physical stress.
The second measure is reducing the spacing between DRAM layers. Without increasing the overall package height, tighter stacking helps accelerate data transfer speeds and lowers the power consumption required to deliver voltage to the top DRAM layers. However, narrowing the interlayer gap introduces new process challenges: the injection stability of Molded Underfill (MUF) material decreases significantly. As a protective and insulating material, uneven filling or voids in the MUF can directly lead to chip defects. To address this, SK Hynix has developed a new packaging technology. The core concept is to achieve narrower DRAM layer spacing while maintaining stable yields without requiring major changes to existing process flows or equipment. The report indicates that recent internal testing has yielded positive results.
Commercial prospects appear promising, but mass production challenges remain. If successfully commercialized, the most significant advantage of this technology is its ability to enhance HBM performance without large-scale capital expenditure. This is particularly important for semiconductor manufacturers seeking cost-effectiveness balance amid intense R&D competition. However, the report cautions that transitioning from the verification phase to mass production still presents challenges related to technological stability and process consistency. SK Hynix is actively advancing related verification work, but a specific commercialization timeline has not yet been announced.
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