The demand for AI computing power is altering the growth trajectory of the semiconductor industry. For decades, chip performance improvements have primarily relied on Moore's Law: making transistors smaller and denser. However, as advanced processes continue to shrink, metal spacing, power consumption, leakage, heat dissipation, yield, and costs are approaching their limits. Simply betting on "smaller nodes" is no longer sufficient.
According to a report by Nomura Securities Asia-Pacific technology analyst Donnie Teng and his team, the growth logic of the semiconductor industry has shifted from increasing transistor density to "combinatorial innovation involving 3D transistors, backside power delivery, and diverse new materials." This statement is the core of the entire research: AI is not only driving GPU demand but is also compelling a fundamental rewrite of chip manufacturing processes.
A more direct investment implication is that materials, consumables, substrates, specialty gases, and compound semiconductors, once considered supporting components, are becoming critical variables determining the performance of advanced chips. Starting around 2027, technologies such as backside power delivery, wafer-bonded NAND, glass core substrates, and photonic SOI will enter a phase of rapid scaling, potentially leading to a systemic revaluation of the materials sector.
Taiwan Semiconductor Manufacturing remains the most significant amplifier in this chain. The expansion of advanced production capacity, the adoption of SoIC hybrid bonding, the introduction of high-NA EUV, and the increase in localized procurement ratios will transmit orders to equipment, materials, and component companies. Unlike the previous semiconductor cycle, this round involves not just a single process upgrade but simultaneous shifts in structure, packaging, and materials.
Moore's Law is not obsolete, but relying solely on scaling is no longer enough.
The issue with advanced processes is not an inability to progress further, but the escalating costs. From 7nm to 3nm and beyond, further compression of metal spacing leads to more severe problems with power consumption, leakage, and heat dissipation. The patterning capabilities of low-NA EUV and DUV are also limited. While multiple patterning can address some precision issues, cost and yield pressures rise accordingly.
Therefore, advanced logic chips are turning to more complex structural innovations. Gate-all-around transistors will continue to evolve toward stacked cFETs, with the core goals of improving gate control over channels and increasing integration density.
Backside power delivery resembles a "rewiring rearrangement." Moving the power delivery network from the front to the back of the wafer, separating it from the signal network, and using wider, lower-resistance metal lines for power supply reduce IR drop and alleviate backend routing congestion. This creates room for further scaling of standard cells.
These changes are not merely conceptual; they directly drive process material consumption. The number of CMP steps in advanced process chips will increase from the traditional 45-55 steps to 55-70 steps, a rise of about 20%-30%. Backside power delivery also requires stacking two wafers, nearly doubling wafer consumption, which in turn boosts demand for wafer thinning, grinding, and bonding.
The timing is also critical: related equipment and material demand will begin to pick up from 2026, enter a rapid scaling phase by 2027, and are expected to become standard for advanced chips by 2030.
High-NA EUV truly drives the upgrade of lithography materials.
High-NA EUV is the core equipment for next-generation advanced processes. Increasing the numerical aperture from 0.33 to 0.55 improves resolution to 8nm, aiming to eliminate the need for multiple patterning at nodes below 3nm, with mass production expected as early as 2029. The price per unit exceeds $400 million.
However, high-NA EUV is not just about purchasing equipment. A higher numerical aperture means photons strike the wafer at shallower angles, requiring thinner photoresist layers to avoid shadow effects. Traditional chemically amplified photoresists, under ultra-thin conditions, lack sufficient etch resistance, photon absorption efficiency, and pattern fidelity.
Metal oxide photoresists thus become a key material. With metal oxides at their core, they offer stronger etch selectivity, higher resolution, and better roughness control, making them more suitable for high-NA processes.
The change in value is evident: current EUV photoresists cost about $5,000 per gallon, while high-NA EUV-specific metal oxide photoresists can reach $10,000 to $40,000 per gallon, representing a 2 to 8-fold increase in unit price.
The upgrade in lithography materials extends beyond photoresists. Mask blank materials also need replacement; traditional tantalum-based absorbers struggle to meet the reflection angle requirements of high-NA processes, with ruthenium and molybdenum-based materials emerging as alternatives. Supporting materials like developers, cleaning solutions, bottom anti-reflective coatings, and edge bead removers will also undergo upgrades.
The next frontier in advanced packaging may be glass substrates.
AI chips are increasingly reliant on advanced packaging because continuously enlarging single chips or stacking more computing power encounters multiple limitations: power consumption, interconnects, heat dissipation, and manufacturing yield.
SoIC hybrid bonding is expected to see a surge in demand between 2026 and 2027, primarily for high-density integration of AI chips and HBM. Compared to traditional micro-bump processes, hybrid bonding enables direct Cu-Cu connections, increasing interconnect density by an order of magnitude and boosting bandwidth from 200 GB/s to 1 TB/s.
It imposes high process requirements: wafer surface flatness must be controlled at the nanometer level, making CMP a critical step; bonding equipment requires precision below 0.2 microns; and cleaning, surface activation, and alignment processes need upgrades. Besi, as a leader in chip-level and wafer-level hybrid bonding equipment, is expected to see orders rebound rapidly from 2026, driven by AI chips, optical communication, and HBM.
Packaging substrates are also changing materials. Glass core substrates, compared to traditional ABF organic substrates, offer a lower coefficient of thermal expansion, higher flatness, better heat dissipation, and lower signal loss, making them more suitable for large-size, high-power, high-speed signal chips.
In projected scenarios, Broadcom may pioneer the use of glass core substrates for switch ASICs by 2027, and Intel is also advancing its development as a core material for next-generation advanced packaging. However, glass substrates are not yet fully proven, with large-scale production still constrained by high costs, issues with RDL dielectric layer delamination and separation, and yield ramp-up challenges.
The real process challenge lies in through-glass vias. Laser drilling, etching, metal filling, and planarization determine final performance. Companies like Ingentec, with patented TGV technology, are entering this supply chain.
Optical communication brings compound semiconductors to the forefront.
The bottleneck in AI data centers lies not only in GPUs but also in communication. High-speed optical modules and CPO co-packaged optics are driving the optical communication industry chain upward, with the proliferation of 1.6T modules and the migration to silicon photonics as two main trends.
Indium phosphide substrates are used for EML and CW laser chips, serving as core materials for optical modules. Due to export controls on indium metal and production yield bottlenecks, indium phosphide supply is expected to remain tight from 2025 to 2027, keeping prices high.
Another route is photonic SOI wafers, used for silicon photonic integrated circuits. Their cost is only 25% that of indium phosphide substrates, making them more suitable for mass production and serving as a core material for CPO solutions. Soitec holds about 70% of the global photonic SOI wafer market share, with companies like GlobalWafers and National Silicon Industry Group Co., Ltd. following suit.
By 2027, demand for photonic SOI is expected to enter a rapid growth phase, becoming the most significant growth driver for the SOI wafer segment.
The supply-demand balance for 12-inch silicon wafers is expected to tighten starting in 2027.
Changes in manufacturing processes driven by AI will re-accelerate silicon wafer demand.
Conventional market demand grows at an average annual rate of about 5%. Capacity expansions by Taiwan Semiconductor Manufacturing, Samsung, and Intel add another 2-3 percentage points of demand growth annually. Three new technologies—backside power delivery, wafer-bonded NAND, and photonic SOI—will contribute an additional 2-3 percentage points of demand annually.
In total, the overall annual demand growth rate for 12-inch silicon wafers approaches 10%.
The supply side cannot adjust as quickly. Silicon wafer capacity expansion is constrained by equipment lead times and capital expenditure cycles, making it difficult to immediately match demand. A supply-demand gap is expected to gradually emerge from 2027, strengthening the pricing power of leading companies like GlobalWafers, Shin-Etsu, and SUMCO, leading to continuous increases in long-term agreement prices. Supporting businesses such as wafer reclaim and test wafers will also benefit.
Taiwan Semiconductor Manufacturing's capacity expansion and localized procurement are catalysts for supply chain scaling.
Taiwan Semiconductor Manufacturing's capital expenditure could reach $70 billion by 2027, with 26 advanced wafer fabs and packaging bases globally undergoing expansion, 18 of which are located in Taiwan, and factories in the US, Japan, and Germany ramping up simultaneously.
The release of advanced capacity will directly drive demand for equipment, materials, and components. More importantly, Taiwan Semiconductor Manufacturing is continuously increasing the proportion of localized and regional procurement for equipment, components, and materials, covering categories such as raw materials, parts, consumables, and facility equipment.
This opens a window for regional suppliers to enter the qualification process. Key areas for localized procurement include lithography support, CMP consumables, specialty gases, silicon wafers, and packaging materials. If material companies from Taiwan and mainland China pass certification, their market share growth could be significantly faster than in a typical cycle.
The industry implementation timeline is clear, with 2027 becoming an inflection point for the entire industry chain.
The timeline for this industry chain can be summarized into key points: 2026: GAA transistors, SoIC hybrid bonding, and InP substrates begin, with small-volume supply emerging. 2027: Backside power delivery, wafer-bonded NAND, and glass core substrates see concentrated volume growth, entering larger-scale production phases. 2028: DRAM-on-logic architecture enters scalable application, driven by edge AI and automotive electronics. 2029-2030: High-NA EUV enters mass production, with metal oxide photoresists and new mask blank materials fully adopted.
The materials segment has underperformed equipment over the past decade, partly because the high unit price of AI chips more easily boosts revenue for the equipment chain, and also because the Moore's Law era favored equipment more, with material demand experiencing greater volatility during industry downturns. Now, change is underway: 3D structures, new materials, and advanced packaging are advancing simultaneously, increasing both material consumption per unit and value.
The most noteworthy aspect of this transformation is that AI has not merely brought a cycle of GPU prosperity; it is pushing semiconductor manufacturing from "process scaling" toward "structural innovation + material substitution + advanced packaging." From silicon wafers to glass substrates, from GPUs to optical communication, the value distribution within the industry chain is being rewritten.
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