Recently, many chip design companies have been facing "closed doors" at wafer fabs, with numerous foundries reporting that securing production capacity for certain mature processes has become increasingly difficult. However, this is not a simple return to the traditional "chip shortage" scenario, but rather a profound chain reaction triggered by the spillover effects of AI. AI is not only monopolizing resources for advanced processes and advanced packaging but is also transmitting pressure to mature nodes through the power and supply chain: data center power consumption is skyrocketing, driving sustained increases in demand for PMICs, power devices, drivers, and more—chips that often rely on 8-inch or mature process capacity. When the supply side simultaneously contracts, mature processes naturally experience a chain reaction of harder-to-secure production slots, maxed-out utilization rates, and price recovery. Furthermore, the AI-driven recovery in the memory market is, through price increases in basic components like NOR Flash, further elevating the comprehensive costs of MCUs and various modules. Behind the scenes, wafer fabs have been quietly active recently. TSMC and Samsung are accelerating the contraction of their older 8-inch production lines, silicon wafer manufacturers are expanding 12-inch capacity, and Powerchip is selling its most advanced new 12-inch fab... A series of seemingly disparate events actually point to the same overarching trend—the semiconductor landscape of 2026 is no longer characterized by simple cyclical fluctuations but is instead a fundamental restructuring of capacity centered on survival.
The first key to understanding this restructuring begins with a seemingly "outdated" protagonist: the 8-inch wafer. On the historical timeline of 8-inch wafers, 2026 is destined to be a watershed year. TSMC and Samsung, the two giants dominating global process technology, are concurrently choosing to shutter some of their 8-inch fabs. In August 2025, TSMC announced it would gradually phase out its 6-inch wafer manufacturing business over the next two years and continue to consolidate its 8-inch wafer production capacity to enhance efficiency. Currently, TSMC still operates one 6-inch fab and four 8-inch fabs in Taiwan for manufacturing chips using mature nodes. TrendForce, citing Taiwanese media reports, indicated that TSMC's 8-inch Fab 5 is expected to cease production around the end of 2027, while its 6-inch Fab 2 will also halt operations in 2027. Similar moves are underway at Samsung. Reports suggest Samsung plans to shut down its 8-inch S7 fab in Giheung, South Korea, with the timeline falling in the second half of 2026, corresponding to a capacity reduction of approximately 50,000 wafers per month. It is crucial to emphasize that this does not signify "Samsung's complete exit from 8-inch"—facilities like S6 and S8 in Giheung will continue operating. However, information from The Elec notes that after S7 goes offline, Samsung's 8-inch monthly capacity will drop from about 250,000 wafers to below 200,000 wafers, and the current utilization rate of its 8-inch lines is approximately 70%, providing a practical basis for phasing out older lines.
So why are both companies "retiring" 8-inch capacity? The reason is not a lack of demand for mature processes, but rather a deep-seated consideration based on economics and platform migration. Firstly, the economics are becoming increasingly unfavorable. Under the same costs for facilities, labor, and maintenance, 12-inch wafers yield more dies and are more amenable to scaling and automation. In contrast, 8-inch equipment faces issues like aging, high maintenance costs, and significant depreciation pressure, inherently resulting in thinner profit margins. TrendForce's analysis also highlights that as key products continue migrating to 12-inch platforms, large-scale operation of 8-inch fabs becomes progressively less economical. Secondly, product platforms are migrating. Categories represented by CMOS Image Sensors (CIS) and Display Driver ICs (DDI) are accelerating their shift to 12-inch platforms. One major reason for Samsung's 8-inch utilization rate being only around 70% is precisely the "migration" of volume products like CIS/DDI. Once these high-volume products depart, the product mix on 8-inch becomes more marginalized, leading to shutdowns and consolidation. Thirdly, the AI siphon effect: In the face of the computing power race, capital flows toward higher returns. Giants are channeling every dollar of budget and every engineer into more lucrative advanced processes and advanced packaging (like CoWoS). On the resource map of these giants, the priority of 8-inch capacity inevitably gets pushed back.
Ironically, the retirement of giants coincides with a resurgence in demand. AI's impact extends beyond cloud computing; it drives exponential growth in demand for power management ICs (PMICs) and power devices. This structural uptick in demand, colliding with a hard contraction on the supply side, directly upsets the supply-demand balance for 8-inch capacity. The retreat of the giants leaves a rich legacy for those who remain. The most immediate effects are rising utilization rates and price increases. As both TSMC and Samsung scale back their 8-inch operations, TrendForce estimates global 8-inch supply will decrease by approximately 2.4% year-on-year in 2026, while the global average utilization rate could climb from 75–80% in 2025 to 85–90%. While the giants chase AI's "quick money," pricing power for mature processes is handed over to the remaining players. According to TrendForce reports, some foundries have already notified customers of plans to raise prices by 5%–20%, and unlike 2025's selective increases on certain platforms, this round of hikes is expected to be broader.
So who stands to benefit? In the short term, second-tier fabs and regional players are most likely to capture the spillover orders. For instance, companies like South Korea's DB HiTek, which specialize in high-mix, low-volume 8-inch capacity (for PMICs/DDIs, etc.), may capture a wave of "order回流" (order return). Some 8-inch capacity in Mainland China is also poised to share in the benefits. In the medium term, 8-inch capacity will not disappear, but its role will transform: evolving from a past mainstay of scale production into a more expensive, more specialized, higher-mix capacity pool. The responsibility for mainstream, scaled manufacturing will shift to 12-inch mature process platforms. Regardless of how strong 8-inch demand becomes, the migration of mature processes to 12-inch wafers is an almost irreversible trend. The commencement of production at TI's Sherman fab is a landmark event signaling this shift. Texas Instruments' latest 12-inch wafer manufacturing base in Sherman, Texas, began production last August, taking about three and a half years from groundbreaking to operation. The significance of this factory lies not in "just adding another production line," but in pushing the underlying logic of analog chip competition further toward manufacturing scale and cost structure: when giants can run mature products on 300mm wafers with higher utilization and automation, the cost floor of the traditional analog market will be redefined.
More interestingly, the 12-inch expansion is not limited to the manufacturing end; upstream silicon wafer suppliers are also ramping up simultaneously. In January 2026, GlobalWafers publicly stated it was preparing for a Phase 2 expansion of its Texas factory. 300mm silicon wafers represent an upstream segment with high capital expenditure and long payback periods. The fact that an upstream player dares to discuss "Phase 2" at this juncture typically implies two things: firstly, stronger certainty in customer demand (at least at the level of contracts, commitments, or long-term cooperation), and secondly, a judgment on the long-term growth potential of the local supply chain. In other words, when upstream materials and downstream manufacturing form a "rolling expansion" in the same region, the capacity migration occurs faster and more decisively, exerting sustained pressure on players still reliant on 8-inch technology with limited expansion flexibility. However, 300mm does not equate to an "automatic victory." On the other hand, Powerchip's (PSMC) decision to sell its fab precisely reveals a harsh reality of the 12-inch era. In January 2026, Micron Technology and Powerchip signed a Letter of Intent for Micron to acquire the P5 fab site in Tongluo, Miaoli, Taiwan, for $1.8 billion in cash. This move exemplifies a typical survival strategy for second-tier players caught between cyclical fluctuations and pressure from giants: prioritize cash flow and shed the burden of heavy assets under low utilization. This P5 factory was built by Powerchip at great cost. According to external reports, the P5 fab's maximum monthly capacity is 50,000 wafers, but currently only equipment for about 8,000 wafers per month is installed, resulting in a capacity utilization rate of only about 20%.
Second-tier manufacturers fear the "depreciation black hole" most. Annual equipment depreciation amounting to billions can easily devour all profits generated from 8-inch lines. Selling the fab not only provides a one-time cash infusion and improves financial flexibility but, more importantly, removes the long-term burden of heavy assets from the balance sheet. This transaction is more than just a sale; the official announcement explicitly mentioned that Micron and Powerchip will establish a long-term partnership, including cooperation on wafer manufacturing related to advanced DRAM packaging. In other words, Powerchip is trading an expensive but inefficient asset for a long-term tie-up with a global DRAM leader, upgrading from selling capacity to participating in collaboration higher up the value chain. This reveals the fate of second-tier foundries: in an era of accelerated expansion of 12-inch mature capacity, lacking the pull of proprietary products or the support of stable utilization, 12-inch capacity itself does not inherently equate to competitiveness; on the contrary, it can become an amplifier of financial and operational pressures. Powerchip's choice resembles a rational maneuver—trading assets for flexibility, and cooperation for an industrial position. For Micron, this is a strategic acquisition using cash to buy time, capacity, and a stronger position in the supply chain—aiming to secure control over supply for the post-2027 DRAM/HBM era. After the acquisition, Micron will take over P5 and gradually introduce equipment, ramping up DRAM production, with "meaningful DRAM wafer output" expected to begin in the second half of 2027. Compared to building a factory from scratch—involving construction, cleanrooms, environmental assessments, utilities, talent, and supporting infrastructure—this approach saves at least 3–5 years.
The gradual contraction of 8-inch capacity by TSMC and Samsung essentially represents a "receding tide" on the supply side for mature processes—but for Mainland Chinese fabs, this opens an extremely valuable window of opportunity: to capture the reallocation of the existing 8-inch market. As the shutdown of older lines like Samsung's S7 progresses and overall 8-inch supply enters negative growth, available capacity for the global power and analog supply chains becomes scarcer. Overseas clients are beginning to search more intensively for alternative capacity, thereby granting leading Mainland players stronger order intake capabilities and pricing leverage. Hua Hong's 8-inch lines have long maintained high utilization rates exceeding 110%, and SMIC has also achieved price recovery during the mature process cycle—this indicates that the so-called "8-inch exit" does not mean demand has vanished, but rather a rearrangement of the supply landscape, bringing a rare wave of profit elasticity and customer onboarding opportunities for Mainland Chinese manufacturers. However, the real determinant of success lies in 12-inch technology: only those who can translate the 8-inch window into the capability for scaled migration of specialized 12-inch processes will be qualified to master the cost curve and customer stickiness in the next mature process cycle. The core objective of 12-inch capacity expansions, such as those by SMIC in Beijing/Shenzhen and the second phase of Hua Hong Wuxi, is not simply "adding capacity." It is to enable key categories originally dependent on 8-inch—like automotive IGBTs, PMICs, BCD/HV processes—to complete their "upgrade," leveraging larger wafer areas, higher automation, and more stable yield ramps to shift mature process competition from "grabbing existing orders" to a new stage of "reshaping cost structures."
Yet, the flip side of the opportunity is a sharper dual pressure: first, time pressure—they must complete the yield ramp and certification for specialized 12-inch processes before the 8-inch红利 (dividend) recedes, otherwise the order window will vanish quickly; second, supply chain pressure—given the ongoing external constraints on key equipment and materials (especially 12-inch silicon wafers), expansion is no longer a matter of "expanding at will." Supply security will directly determine the capacity ceiling. Simultaneously, the trend of giants like TI using scaled 12-inch mature processes to "crush costs" is continuously lowering the industry's cost floor, forcing Mainland Chinese manufacturers to move beyond 8-inch price competition and compete on higher-value specialized processes, platform migration, and delivery reliability. Therefore, the strategy for Mainland Chinese fabs to break through must be more clear-eyed: capitalize on the 8-inch红利, but do not get bogged down in a prolonged battle; the real bet should be on the "upgrade migration project" for specialized 12-inch processes—using high 8-inch utilization as cash flow support and a customer entry point, locking in migration paths with long-term frameworks, prioritizing the mastery of replicable BCD/HV, power, and automotive peripheral combinations, while proactively integrating constraints related to key materials and equipment into capacity planning. By standardizing platforms and pursuing domestic substitution in parallel, they can transform "window-of-opportunity orders" into "long-term capabilities." In other words, this round of 8-inch exit offers Mainland Chinese manufacturers not just order spillover, but a ticket to enter the new order of 12-inch mature processes.
In this capacity restructuring triggered by the AI tidal wave, we are witnessing a "great handover" in the global semiconductor landscape. Firstly, a handover among players: giants like TSMC and Samsung are decisively withdrawing from the red ocean of mature processes, transferring the existing 8-inch orders and pricing prerogative to Chinese domestic fabs and mid-sized foundries with greater scale resilience. Secondly, a handover of wafer sizes: mature processes are undergoing a qualitative transformation, an "upgrade" from 8-inch to 12-inch, where the generational gap in efficiency and cost is delivering a thorough dimensionality reduction attack on the old model. Thirdly, a geographical handover: the industry's center of gravity is accelerating its shift from the decentralized global collaboration of the past three decades towards localized manufacturing clusters represented by Texas and Arizona, redefining supply chain security through physical proximity. Semiconductor history proves that behind every wave of capacity crunch lies a brutal iteration of productivity. For manufacturers navigating this transformation, the beginning of 2026 is a watershed moment: giants are sealing off future competitive highlands through divestitures and mergers; second-tier players are seeking survival niches amid the pains of asset maneuvering; and Mainland Chinese manufacturers are racing against time on the upgrade track with unprecedented speed.
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