In the current race for co-packaged optics (CPO) in data centers, Taiwan Semiconductor Manufacturing (TSM) has gained an early advantage with product progress from Broadcom and Nvidia. Meanwhile, Samsung may be placing its bets on the next phase of development.
Recent on-site research by PhotonCap indicates that CPO for switches has officially moved from technical validation to the customer deployment stage.
TSM's manufacturing and advanced packaging capabilities in this field have already been validated by the first wave of top-tier commercial projects. However, the future competitive landscape is far more complex than the current switch-based CPO.
As optical I/O moves deeper into the package containing heterogeneous compute chips (XPU) and high-bandwidth memory (HBM), the company that can master the co-design of these three elements will reshape the competitive dynamics of the entire industry.
Samsung Electronics Senior Vice President Won-Kyoung Choi stated at Nano Korea that the company is developing 2.xD advanced packaging, aiming to integrate HBM, logic chips, and silicon photonics chips into a single package. This direction is precisely targeting future optical I/O for AI compute packages.
TSM's Current Lead in "Switch CPO"
In the current CPO market, TSM is the undisputed leader.
Research shows that Broadcom's 102.4Tbps CPO Ethernet switch, based on TSM's COUPE platform, has been sampled to early customers.
Concurrently, Nvidia's Quantum-X photonic switch has begun shipping, and its Spectrum-X Ethernet photonic switch has entered production, with initial adopters including CoreWeave, Lambda, and Oracle.
The commonality of this generation of products is that the optical engine is placed near the switch ASIC. The core manufacturing foundation is TSM's mature silicon photonics technology and SoIC 3D stacking capability.
In this architecture, the competition focuses on the stacking, bonding, and integration of the photonic integrated circuit (PIC) and electronic integrated circuit (EIC) with the switch package. HBM is not a necessary component at this stage.
In contrast, Samsung's public "Turnkey CPO" roadmap targets 2029. Measured by current switch CPO shipment volumes and customer validation, Samsung has yet to establish a commercialization pace on par with TSM.
Power Concerns Drive Optical Engines Closer to Compute Chips
The primary driver for moving optical I/O from the traditional board-level to inside the package is power consumption.
Materials prepared by Samsung Foundry for OECC 2026 reveal a key progression: when pluggable optical modules are deployed at the board level, energy per bit is about 10pJ; when the optical engine is placed on a substrate near the switch, consumption drops to about 5pJ; if optical I/O moves further to an interposer near the XPU, consumption can be significantly reduced to about 2pJ.
The core logic of this change lies in "shortening the electrical signal transmission distance." The closer the optical engine is to the compute chip, the shorter the electrical link, reducing the signal conditioning needed to compensate for board-level trace and connector losses.
Therefore, advanced packaging becomes the critical link in translating "physical power advantages" into "commercial product advantages." This does not mean CPO will immediately kill pluggable modules; both will coexist long-term for different transmission distances and power budgets.
However, Samsung's data forecasts a trend, with the pluggable optics market growing over 25% annually, while the CPO market is growing at over 150% per year. Capital and R&D resources are pouring into highly integrated optical architectures.
Two CPO Architectures and Samsung's Divergent Strategy
Conflating "switch CPO" with "XPU-HBM optical I/O" severely underestimates the complexity of the next phase. These are two distinct architectures.
The first is the current mainstream "switch CPO," where the optical engine sits next to the switch ASIC, as seen in Broadcom and Nvidia products. It addresses interconnect power and signal integrity in high-bandwidth switching scenarios. TSM's moat lies in silicon photonics, advanced bonding, and switch packaging integration.
The second is optical I/O packaging for "XPU-HBM systems." Its structure places the XPU (or GPU), HBM, and the optical engine containing PIC and EIC together on an interposer. Here, optical I/O is no longer a peripheral component of the switch but becomes an integral part of the "compute package."
Samsung's recently proposed 2.xD advanced packaging targets this direction. The plan is to integrate HBM, logic chips, and silicon photonics chips in the same package, using panel-level RDL interposers to expand system-in-package capability, meeting the massive bandwidth throughput demands of AI data centers.
For investors, the competitive logic differs: the former tests singular manufacturing and packaging processes; the latter requires deep, joint optimization of compute, memory, optics, and packaging from the "initial design phase."
Samsung's Potential Edge and the Multi-Die Yield Challenge
Samsung's greatest potential differentiating advantage is its "trinity" business portfolio, encompassing HBM, logic chip foundry services, and a silicon photonics platform.
While TSM possesses top-tier logic foundry services, silicon photonics, and CoWoS packaging, it does not produce HBM itself.
Samsung, however, can connect HBM to its foundry capabilities via SF4 base dies and has established its own silicon photonics platform. This means Samsung could theoretically perform joint co-design of the HBM interface, logic I/O, optical engine, and thermal management internally, without relying on external memory suppliers.
2.xD packaging faces extremely stringent "multi-die yield" tests. When logic chips, HBM, PIC, EIC, and interposers are packed into one package, the failure of any single component can scrap the entire expensive package.
Increasing chip counts, larger package areas, and greater bonding complexity are exponentially amplifying yield pressure and cost risks.
Meanwhile, competitors are not idle. TSM is advancing the integration of COUPE with CoWoS packaging to access HBM through its mature external ecosystem.
Separately, memory giant SK Hynix is aggressively building advanced packaging capabilities, with a $3.87 billion advanced packaging fab in Indiana set for mass production in 2028, and has included CPO in its memory system technology roadmap.
Cross-domain collaboration between optics, memory, and packaging is becoming a focal point for the entire industry chain.
Orders Are the Ultimate Test of Success
TSM has won the first round in switch CPO, its advantage built on tangible customer sampling, product shipments, and mass production progress.
Samsung is betting on the next battle: attempting to leverage its vertical integration in HBM, logic, and silicon photonics to overtake competitors in the AI compute packaging arena.
However, the market should not equate a "technology roadmap" with a "commercial moat."
Over the next 12 months, the single most important signal to track is whether a named customer design win emerges, explicitly requiring the integration of HBM, logic chips, and optical I/O in a single package to be manufactured by Samsung.
If such an order materializes, Samsung's "trinity" would transform from a paper asset into a genuine commercial weapon.
If it fails to materialize, then TSM's flexible path, built on leading-edge process technology and an external HBM ecosystem, will likely remain the safest choice for AI giants.
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