The introduction timeline for hybrid bonding technology in the High Bandwidth Memory (HBM) sector is being reconsidered by both Samsung Electronics and SK hynix. As HBM thickness standards gradually relax and alternative solutions for thermal management emerge, the commercial deployment of this once highly anticipated next-generation packaging technique has been successively postponed.
According to a Monday report from the Korean tech media outlet ZDNet Korea, industry observers note that the point at which hybrid bonding is fully applied to next-generation HBM may be later than previously expected. The two companies initially anticipated introducing the technology as early as in HBM4 (the sixth generation of HBM), but ultimately continued with the conventional thermal compression (TC) bonding solution.
Current industry forecasts suggest the adoption node for hybrid bonding may be delayed until the 16-layer HBM4E (the seventh generation of HBM), with some industry insiders believing the actual timeline could be pushed back even further.
This change directly impacts the HBM supply chain and related packaging equipment manufacturers. The delay in hybrid bonding technology implies an extended lifecycle for the existing TC bonding process, and the capital expenditure rhythm for hybrid bonding equipment and materials will also be adjusted accordingly.
Relaxed Thickness Standards Diminish Core Advantage of Hybrid Bonding
The primary advantage of hybrid bonding technology lies in its ability to directly connect the copper lines of each DRAM layer without requiring bump structures, making it easier to compress the overall HBM thickness while improving thermal performance and power efficiency. However, the market urgency for these advantages is diminishing.
HBM industry thickness standards have shown a trend of gradual relaxation. The standard thickness was 720 micrometers for HBM3E (the fifth generation) and has been increased to 775 micrometers for HBM4, primarily due to the increase in stacking layers from 8 and 12 layers to 12 and 16 layers. It is reported that the international semiconductor standardization body JEDEC is currently discussing further relaxing the thickness upper limit for products like 20-layer stacked HBM5 from 900 micrometers to approximately 1000 micrometers. Once thickness constraints loosen, the inter-layer spacing between DRAMs no longer needs to be compressed to the limit, thereby reducing the technological pressure on TC bonding.
Simultaneously, the demand timeline from key clients like NVIDIA for highly-stacked HBM has also been pushed back. A memory industry source A stated, "Currently, discussions between clients and memory manufacturers regarding 16-layer HBM are not active. For now, it is highly likely that 12-layer products will continue to dominate even within HBM4E."
Emerging Thermal Alternatives Prompt Companies to Explore New Paths
Improving thermal performance is another major selling point of hybrid bonding—removing underfill material with low thermal conductivity helps enhance HBM thermal characteristics. However, Samsung Electronics and SK hynix have each developed alternative thermal management technologies that do not rely on hybrid bonding.
The core of both companies' solutions involves integrating an independent thermal device next to the HBM core chip. Samsung Electronics has named its solution the Heat Path Block (HPB), while SK hynix calls its version iHBM (ICE HBM). Both companies are currently testing the application of these technologies for HBM5.
A packaging industry professional stated, "Configuring a thermal device next to the HBM core chip is not technically difficult, and commercialization should not face obstacles. From the memory companies' perspective, this is a stable choice."
I/O Density Bottleneck May Become the Ultimate Driver for Hybrid Bonding
Despite the short-term delay in the adoption timeline, research and development work on hybrid bonding by Samsung Electronics and SK hynix is expected to continue. The driving force comes from the explosive growth demand for I/O density in the long-term evolution path of HBM.
HBM4 has already doubled the number of I/Os from 1024 in HBM3E to 2048, significantly narrowing the internal HBM pitch. TC bonding involves lateral diffusion when bumps melt, which the industry deems difficult to support for higher-density I/O implementation. Packaging industry source C pointed out, "In the medium to long term, the industry is discussing doubling the I/O count again to 4096 starting from HBM5E. At that point, the I/O pitch will be extremely tight, making hybrid bonding a necessary option."
This indicates that hybrid bonding technology is not being abandoned but rather postponed—its true commercial window may reopen alongside the critical breakthrough in I/O density as HBM generations evolve.
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