NVIDIA's supply chain signals from the Berlin GTC conference are reshaping the Asia-Pacific semiconductor backend landscape, with Bank of America Securities arguing that the core bottleneck in AI infrastructure has shifted from chip design to packaging and testing capacity, while accelerating deployment of co-packaged optics (CPO) opens a new growth track.
According to a research report released by BofA Securities on October 22, NVIDIA (NVDA) confirmed at the Berlin GTC on October 21 that its Vera Rubin GPU and CPU have entered full mass production, and announced deepened partnerships with several key outsourced semiconductor assembly and test (OSAT) vendors covering advanced packaging, testing, CPO and substrates. NVIDIA made major capacity commitments to ASE/SPIL, KYEC and Amkor respectively, with combined capital involved exceeding US$4 billion.
These arrangements point directly to the most prominent contradiction in the current AI supply chain 鈥?insufficient backend capacity. BofA Securities noted that NVIDIA is accelerating consignment of equipment to OSAT vendors to drive capacity ramp-ups, while also speeding up CPO deployment, with related equipment demand expected to see an inflection-point surge in 2027.
NVIDIA Locks In Backend Capacity With Large-Scale Commitments
The cooperation details disclosed at the Berlin GTC are considerable in scale. According to the BofA Securities report, NVIDIA reached an agreement with ASE/SPIL aiming to expand optical engine (OE) capacity 15-fold by mid-2027 and double it again by the end of 2028. It also signed a US$1.1 billion prepayment agreement with KYEC to support the construction of a new testing facility in the United States (expected to start production in April 2027) and to expand its Singapore testing operations (expected to begin mass production in February 2027). Additionally, it signed a US$3 billion agreement with Amkor targeting more than a 300% increase in South Korea interposer capacity by the end of 2028.
BofA Securities believes the core logic behind these arrangements is "customer funding to protect expansion," with NVIDIA transferring capacity expansion risk onto itself through prepayments and equipment consignment, thereby accelerating the ramp-up pace of OSAT vendors. The report estimates that if ASE/SPIL's optical engine capacity expansion proceeds smoothly, this single business could contribute about US$1 billion in revenue to ASE in 2028.
Testing Segment: Wafer Probing and System-Level Testing Emerge as New Focus
In the testing segment, BofA Securities pointed out that NVIDIA aims to double its testing capacity, but the incremental opportunities are mainly concentrated in end wafer probing and system-level testing (SLT), rather than final testing 鈥?the latter already has sufficient capacity for the volume production of Vera Rubin and Mellanox network switch chips.
The key factor driving rapid growth in testing demand is the substantial extension of test time per chip, rather than a simple increase in the number of tests. The report takes a cautious view of KYEC's US investment, noting that its new US facility will initially add only about 100 test machines, and its Singapore operations are also relatively limited in scale, mainly serving HPC customers seeking to reduce geopolitical risk.
CPO Acceleration: Equipment Demand Expected to Reach Inflection Point in 2027
Co-packaged optics (CPO) was another key theme of this GTC. BofA Securities said NVIDIA's plan to accelerate CPO deployment aligns closely with supply chain feedback 鈥?related equipment demand is expected to grow 10-fold in 2027, with the adoption inflection point anticipated in the fourth quarter of 2027.
NVIDIA also announced that it is diversifying packaging sources for its Vera CPU from Amkor/TSMC to ASE, and extending ASE/SPIL's role from GPU substrate assembly to CPO processes. BofA Securities believes this strategic adjustment not only expands ASE's business boundary but also creates new market space for toolmakers with CPO equipment supply capabilities. Beyond CPO, equipment demand related to 2.5D packaging (such as CoWoS, FoCoS, EMIB-T) and 3D packaging (such as SoIC, WoW) is also benefiting from the capacity expansion needs of multiple ASIC/GPU/CPU/network switch chip customers.
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