According to insights from semiconductor analysis firm SemiAnalysis, Alphabet's next-generation TPU, codenamed Humufish, is set to abandon Taiwan Semiconductor Manufacturing's CoWoS packaging in favor of Intel's EMIB-T technology.
Currently, TSMC's CoWoS serves as the industry's default standard for AI chip packaging. A successful migration of a flagship product from a leading tech giant like Google to Intel's packaging ecosystem would represent a significant challenge to TSMC's market position. SemiAnalysis stated on platform X that the shift is notable precisely because CoWoS is the default choice, making a flagship component's move to an alternative solution worthy of attention.
Core Technical Distinctions
The fundamental difference lies in the physical interconnect path. CoWoS places all dies on a large silicon or RDL interposer. In contrast, Intel's EMIB technology embeds small silicon bridges directly into the organic substrate, creating connections only where needed between chips.
Overcoming Reticle Limits and Cutting Costs
TSMC's CoWoS silicon interposer is printed using lithography, making its physical size strictly constrained by reticle limits. SemiAnalysis explains that the monolithic version's (CoWoS-S) limit is about 3.3 times the reticle size, which is why TSMC is moving to CoWoS-L. EMIB is not bound by reticle limits, making it a far more scalable technology.
Beyond size breakthroughs, cost and efficiency are key drivers. EMIB completely removes the expensive interposer, leading to significantly lower packaging costs. A more intuitive difference is seen in silicon utilization. Wafers are circular; cutting large interposers from them results in substantial waste at the edges, with yield decreasing as size increases. In comparison, tiny silicon bridges can be densely packed with almost no waste. This choice also provides buyers with a second supplier beyond TSMC.
Vertical Power Delivery and Next-Gen HBM Compatibility
The Humufish chip specifically uses EMIB-T technology, where the "T" stands for Through-Silicon Via. This design addresses power delivery pain points in traditional packaging. SemiAnalysis explains that standard EMIB has no vias in the silicon bridge, forcing power to travel around it through the substrate, which strains the power delivery network. EMIB-T delivers power vertically directly through the silicon bridge and adds capacitors and ground layers for cleaner power. This architectural upgrade is intended to allow the chip to adapt to next-generation HBM and higher-bandwidth interconnect requirements.
Architectural Suitability and Production Challenges
Addressing market discussions about TSMC's CoWoS-L also using local silicon bridges, independent analyst Nutty points out that CoWoS-L adds a global RDL layer on top of the silicon bridge structure. While this increases routing flexibility, it also adds area and process complexity. For a chip like Humufish, which seems optimized for inference and agent workloads, data flow may be more structured. In such cases, EMIB's approach of placing high-density links only where needed is more logical than paying for full-package routing flexibility. Nutty believes this underscores the significance of EMIB-T: it can reduce silicon usage and packaging costs while acting as a second supplier outside the constrained CoWoS ecosystem.
Production Yield as the Critical Test for Intel
Despite the architectural appeal, execution remains the biggest unknown. As one commenter noted, showcasing yield is crucial before touting cost savings. SemiAnalysis warns that while standard EMIB has been shipping at scale for years, EMIB-T is new technology, and silicon bridges that provide power are more difficult to scale in manufacturing. The advantages will only materialize if Intel can ramp yields and volume as planned. If Intel faces delays, Google's fallback option remains the capacity-constrained CoWoS. The success or failure of this technological migration will directly test the real-world delivery capability of Intel's advanced packaging.
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