How Siemens EDA Empowers Commercialization in the Chiplet Revolution?

The global semiconductor industry is shifting from a protracted race for speed to a new paradigm centered on innovation. In this revolution, Chiplet technology has taken the spotlight, advocating for the decomposition of complex systems into modular small chips and their heterogeneous integration through advanced packaging technologies, thereby opening a path to higher performance density. As design complexity grows exponentially, Chiplet technology demands deep collaboration among EDA software providers, IP suppliers, foundries, and packaging houses. Consequently, the rise of Chiplet technology is, in essence, an ecosystem innovation revolving around "system-level optimization." Against this backdrop, the role and capabilities of EDA software, the cornerstone of chip design, urgently need to evolve. The industry requires not just point-tool innovation but holistic solutions capable of tackling systemic challenges.

Traditional design flows follow a linear mindset of "chip first, then packaging, followed by board-level," making it difficult to conduct cross-domain trade-offs early on. A seemingly perfect decision at the chip level could potentially lead to unforeseen consequences at the packaging or system level. Only by breaking through these barriers can the full potential of Chiplets be truly unleashed from a global perspective. Faced with complex, intertwined system-level challenges, optimization of any single point tool appears insufficient. The entire Siemens EDA design flow is based on the concept of System Technology Co-Optimization (STCO), running through the entire design, verification, and manufacturing process of 3D ICs, pursuing overall optimization at the system level.

Siemens EDA provides a full-flow solution for Chiplet design, from architecture planning to sign-off verification: In the system architecture design phase, Innovator 3D IC™ Integrator (i3DI) can build a 3D digital twin containing chiplets, interposers, substrates, and PCBs, supporting early architecture exploration and pre-simulation evaluation. In the logic verification phase, Veloce CS combines hardware emulation acceleration, enterprise prototyping, and software prototyping for rapid iteration early in development. In the physical design phase, the chip layer uses Aprisa™/Tanner™ for place-and-route, while the system layer utilizes PCB layout and Innovator 3D IC Layout (i3DL), with i3DL capable of efficiently handling the complex interposer and substrate designs in 2.5D/3D structures. In the physical verification phase, the Calibre® platform extends the single-die "golden" DRC/LVS standards to multi-die and 3D stacking scenarios. In the physical test phase, the Tessent™ platform covers multi-die and 3D structures, providing comprehensive test solutions to ensure system reliability.

Notably, addressing the electro-thermal-mechanical multi-physics coupling challenges in 2.5D/3D IC design, Siemens EDA offers a complete closed-loop analysis solution. This solution covers three key areas: signal and power integrity, thermal analysis, and mechanical stress analysis. Signal and Power Integrity are verified electrically using chip-level tools like Calibre mPower and system-level tools like HyperLynx™ SI/PI. Thermal Analysis leverages Calibre 3DThermal for automated, full-flow modeling, enabling highly efficient and accurate thermal simulations. Mechanical Stress Analysis utilizes Calibre 3DStress for transistor-level precise analysis of thermo-mechanical stress and warpage. This integrated flow effectively simulates the complex interactions of "power consumption generating heat, heat causing deformation, and stress affecting electrical properties," allowing designers to perform co-optimization in a unified environment, thereby ensuring the system meets stringent requirements for both performance and reliability.

Through the STCO philosophy and full-flow tool support, Siemens EDA provides the industry with a "compass" to navigate the complexities of Chiplets, not only guiding designers to confidently address local challenges but also leading them towards the broad prospects of system-level high efficiency. Advanced packaging technology is the key that turns the Chiplet concept into reality; each iteration of packaging processes directly propels Chiplet architectures towards greater efficiency, complexity, and cost-effectiveness. In this process, the ability of EDA tools to anticipate and respond to manufacturing requirements is particularly crucial.

As a founding member of the TSMC 3D Fabric alliance, Siemens EDA directly participates in defining related design flows and standards, with its toolchain adapted for TSMC's advanced packaging processes. Furthermore, Siemens EDA supports the 3Dblox open standard proposed by TSMC, which provides a unified description for design behavior and specifications across the entire Die-to-Package hierarchy, and the relevant toolchain has received official certification. In specific collaborations, Siemens provides TSMC with certified automated design flows for its 3D Fabric technology, namely, automated workflows for TSMC's InFO packaging technology, based on Siemens' advanced packaging integration solutions. This automated design flow is supported by the heterogeneous integration cockpit functionality of Innovator 3D IC Integrator, including Innovator 3D IC Layout (i3DL) (formerly named Xpedition Package Designer, officially renamed in October 2025), HyperLynx DRC, and Calibre nmDRC software.

Beyond collaboration with TSMC, Siemens EDA has also cooperated with ASE to complete the development of an Assembly Design Kit (ADK), assisting customers with the design of ASE's fan-out packaging and 2.5D interposer Middle-End-Of-Line (MEOL) routing. By adopting Siemens EDA's Xpedition Substrate Integrator software and Calibre 3DSTACK technology, and integrating ASE's design flow (SiP-id), this co-developed process can reduce the packaging planning and verification cycle for 2.5D/3D ICs and FOCoS by approximately 30% to 50% per design cycle. In addition to system-level collaboration and manufacturing empowerment, Siemens EDA adopts a multi-pronged approach, deeply participating in and promoting the construction of the Chiplet ecosystem. The company acts not only as a technology provider but also strives to be a key node in industrial interconnection, comprehensively strengthening the technical foundation for Chiplets from design to manufacturing through standard setting, industry linkage, and academic research.

Siemens EDA actively participates in the formulation of Chiplet industry standards promoted by the Open Compute Project (OCP). Leveraging OCP's open collaboration mechanism, upstream and downstream enterprises in the industrial chain jointly participate in standard development. As a representative in the EDA field, Siemens EDA is deeply involved in establishing standards for key tools and related specifications involved in Chiplet applications, promoting efficient and orderly industry development from the source. To ensure its toolchain can precisely respond to rapidly iterating manufacturing processes, Siemens EDA has established a normalized industrial collaboration mechanism.

Furthermore, facing the long-term challenges brought by Chiplet technology, Siemens EDA places high importance on collaboration with academia and research institutions. Through direct partnerships or authorized distributor models, the company has established regular cooperation mechanisms with numerous renowned universities and research institutions worldwide, engaging in tool collaboration and technical discussions to grasp future technology trends, thereby ensuring its tools are prepared for future challenges. During this critical period where Chiplet technology is reshaping the semiconductor landscape, Siemens EDA, through its multi-dimensional strategy of system-level collaboration, manufacturing empowerment, and ecosystem co-construction, provides solid support for the commercialization of this complex technology. This not only reflects the foresight of an industry pioneer but also systematically aims to ensure that its toolchain, as Chiplet technology enters the phase of large-scale application, assists the global semiconductor industry in efficiently stepping into a new era of heterogeneous integration.