As AI computing power continues to expand, the logic driving semiconductor capacity expansion is moving beyond chip and wafer fabrication into advanced packaging, optical interconnect, and testing. During SEMICON Taiwan 2026, research conducted by Citi, Nomura, and UBS highlighted six major themes from the show: advanced packaging evolving toward 3D system integration, ongoing CoWoS capacity expansion with a shift toward OSAT providers, accelerated CPO mass production, testing emerging as a new bottleneck, extended lead times for critical equipment, and further maturation of the AI ASIC ecosystem.
Each of the three institutions brought its own focus. UBS zeroed in on TSMC's 3DFabric technology and advanced packaging expansion, raising its end-2027 CoWoS capacity forecast to 260,000 wafers per month. Citi concentrated on the CPO manufacturing stage, emphasizing active coupling and automated bonding. Nomura, meanwhile, directed its attention to testing and equipment, suggesting that post-EIC/PIC bonding tests could become the bottleneck for CPO volume production, and noting that lead times for some equipment have already stretched to two years.
From an industry trend perspective, advanced packaging is transitioning from a standalone packaging technology toward 3D system-level integration, and the core challenge for CPO has shifted from technical validation to large-scale manufacturing and testing. As AI chip performance improves, the importance of packaging, optical interconnect, and testing continues to rise, with industry capacity expansion extending further into the back-end.
In tandem, constraints on equipment and fab capacity are beginning to surface, and AI ASICs have emerged as a fresh growth driver. Overall, the research from these three institutions points to a common shift: AI semiconductor expansion is moving from simply increasing front-end output to a full-chain capacity build-out, with packaging, CPO, testing, and equipment poised to become the critical links in the next phase.
TSMC's Roadmap: From CoWoS to 3D System Integration
TSMC showcased its 3DFabric roadmap aimed at tackling AI compute growth, with advanced packaging and optical interconnect serving as two key pillars. According to a UBS report, TSMC's 5.5x reticle-size CoWoS has already entered mass production with yields exceeding 98%. By 2028, the company plans to expand to a 14x reticle size supporting 20-layer HBM stacks, with a target of 24-layer HBM support by 2029.
Panel-level packaging is also accelerating. UBS pointed out that equipment suppliers are gaining confidence in TSMC's CoPoS (310×310mm²) production capabilities. TSMC aims to finalize process and equipment selection by mid-2027, with mass production slated for 2028.
Notably, TSMC appears cautious about its CoWoS expansion pace in the second half of 2027, with some CoW outsourcing work likely to be increasingly handled by ASE. This signals that advanced packaging capacity growth is spilling over from TSMC's internal operations to OSAT players.
Optical interconnect represents another avenue for TSMC's 3DFabric to extend into system-level integration. UBS noted that TSMC's COUPE roadmap targets 200G per channel by 2026 and aims to reach 400G per channel by 2030.
The underlying tension is that AI compute capacity is growing faster than system I/O bandwidth. A TSMC speaker pointed out that AI computing demand is rising roughly 3x every two years, while I/O bandwidth grows at only about 1.4x over the same period. As transmission frequencies and distances continue to increase, the limitations of copper interconnect become more pronounced, making optical interconnect a key solution to system-level communication bottlenecks.
CPO Manufacturing: Testing Emerges as the Key Production Bottleneck
As CPO moves from technical validation to volume production, the challenges facing the supply chain are evolving: the question is no longer simply whether it can be done, but whether it can be done reliably and efficiently at scale.
Citi noted that CPO manufacturing involves integrating multiple components, including EIC, PIC, lenses, and optical fiber/FAU, with active coupling requiring real-time optical power feedback and multi-axis positioning. Moving into high-volume production, the industry will need to further improve alignment speed, parallel processing capabilities, and automated bonding precision.
Testing has emerged as another major bottleneck. Nomura zeroed in on Insertion 2, the testing step that follows wafer bonding of EIC and PIC. Given the currently low testing throughput, the industry has begun discussing whether this step can be skipped entirely.
However, Nomura argued that while eliminating Insertion 2 could shorten production cycle times, certain tests cannot be covered by subsequent stages, making this step still valuable for assessing wafer yields and clarifying supply chain accountability. In other words, the trade-off between testing efficiency and test coverage is becoming a challenge that CPO mass production must address.
UBS, for its part, expects the industry to gradually streamline Insertion 2 while increasing reliance on Insertion 3, which involves testing individual optical engines. Testing equipment maker Chroma ATE suggested at the show that CPO testing may shift toward a "shift-to-middle" approach: for high-density scaled-out switches, a defect in any single optical engine could scrap the entire CoWoS-level package, making 100% known-good verification at Insertion 3 a potential prerequisite for volume production.
Comments