Intel officially showcased its next-generation server processor, Diamond Rapids, at Hot Chips 2026, featuring up to 256 P-cores and a new Fan-out Fabric architecture as its key selling points. The company is positioning the product as infrastructure for enterprise-level AI agents, directly confronting intensifying competition from AMD and Arm.
Diamond Rapids will be built using Intel's 18A-P process node, supporting up to 1.6TB/s of memory bandwidth, 128 PCIe Gen 6 lanes, and CXL 3.0, delivering a core count increase of over 50% compared to the previous-generation Xeon 6. Intel CEO Lip-Bu Tan has recently hinted that the product roadmap could be accelerated, driven by rising CPU demand from AI agent workloads.
The debut comes amid a rapidly evolving landscape in the data center CPU market. AMD is offering 256-core "Zen 6" processors with its EPYC Venice series, while Nvidia is advancing a dual-track CPU strategy covering both x86 and Arm architectures. Intel's dominant position in the server market is facing mounting pressure from multiple fronts.
New Architecture: Fan-out Fabric Reshapes Chip Design
The most significant technological shift in Diamond Rapids is what Intel calls its "first CPU to adopt a Fan-out Fabric architecture." This design partitions the chip's functions into four major modules: Scalable Compute Building Blocks, a centralized I/O and memory Fabric Hub, a unified memory fabric, and a flexible I/O fabric.
From a physical construction standpoint, the entire chip is assembled from 22 individual dies, including 16 core chiplets built on the Intel 18A-P process, 2 Fabric Hubs based on the Intel 3 process, and 4 base tiles manufactured on the Intel 3-T process. These components are connected through Foveros Direct 3D hybrid bonding and UCIe-S copper interconnect interfaces. This design approach closely resembles AMD's EPYC Venice architecture, which arranges multiple CPU chiplets around a large I/O die.
A key distinction from the previous Granite Rapids generation is that Diamond Rapids separates memory controllers from the compute chiplets, integrating them into the Fabric Hub to enable more flexible scalability. Each compute building block contains 16 cores and incorporates a 3D Xbar that connects the cores to the last-level cache (LLC) on the base tiles. The entire chip shares a 1.28GB LLC, with each base tile carrying 320MB.
Core Specifications: 256 Cores Align with AMD, Memory Bandwidth Leaps Forward
In terms of core count, Diamond Rapids scales to a maximum of 256 P-cores based on the Panther Cove-X architecture, arranged as four compute building blocks each containing four core chiplets. This represents a doubling of the maximum 128 cores found in Xeon 6, matching the 256-core ceiling of AMD's EPYC Venice.
On the memory subsystem side, Diamond Rapids supports a 16-channel design, reaching 12,800 MT/s speeds with MRDIMMs and 8,000 MT/s with standard DDR5, delivering peak memory bandwidth of 1.6TB/s. For I/O, the chip provides 128 PCIe Gen 6 lanes and supports CXL 3.0, offering ample expansion capabilities for storage and network-intensive scenarios. Additionally, the chip introduces a next-generation Advanced Performance Extensions (APX) instruction set and enhanced Advanced Matrix Extensions (AMX) to accelerate AI inference and matrix operations.
Notably, Diamond Rapids does not support Simultaneous Multi-Threading (SMT), a feature that will return in its successor, Coral Rapids. On the platform side, the chip uses an LGA 9324 socket with a maximum TDP of 650W.
Product Roadmap: Coral Rapids Accelerated, Custom SKU for Nvidia in the Pipeline
Looking at the product roadmap, the next step after Diamond Rapids is Coral Rapids, expected to launch in mid-2028, which will reintroduce SMT support and adopt an 8-channel memory platform. Lip-Bu Tan recently stated that the timeline for this product line could be moved up, given the rapid increase in demand for general-purpose processors driven by AI agent workloads. Notably, Intel had previously planned an 8-channel version of Diamond Rapids but ultimately scrapped it to concentrate resources on the 16-channel variant.
In terms of competitive and collaborative dynamics, Intel is working on a custom partnership with Nvidia, with a custom x86 SKU featuring an NVLink interface reportedly in development and slated for delivery to Nvidia. This move would directly integrate Intel's Xeon architecture into Nvidia's CPU diversification strategy, while Intel simultaneously competes head-to-head with Nvidia's Vera and AMD's Venice in the data center CPU market.
The core logic behind Intel's bet is that the AI Agent era will elevate the strategic value of general-purpose processors within AI infrastructure, opening up a larger market space for the Xeon series. Whether this assessment holds true will largely depend on Diamond Rapids' production timeline and its actual delivery performance.
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