The increasing size of AI chips is redefining the limits of packaging materials.
Taiwan Semiconductor Manufacturing (TSMC) has recently disclosed progress on its "glass substrate" technology application for the first time, confirming collaboration with major ABF substrate supplier Ibiden and panel maker Innolux to jointly verify the feasibility of integrating glass substrates into the next generation of CoWoS advanced packaging.
Simultaneously, TSMC indicated that competition in advanced packaging is gradually shifting from the CoWoS arena to the Chip-on-Panel-on-Substrate (CoPoS) battlefield, and it is proactively working to establish a complete ecosystem. Supply chain sources point out that intensifying pressure from customer technical specifications and capacity demands, as well as from competitors like Intel and Samsung, is forcing the typically "cautious and not aggressive" TSMC to accelerate its technology adoption pace.
Performance Advantages of Glass Substrates in Large-Scale Packaging
The test sample used by TSMC employed a 0.8mm glass core substrate, with a packaging specification of 5x Reticle CoW and an overall package size of 85x110mm, which is at the level of large AI GPU packaging.
Verification results show that compared to organic substrates, the glass substrate demonstrated significant improvements across several key metrics:
Chip-on-Package (COP) warpage improved by 16%. Package flatness directly impacts yield, and as AI GPU sizes continue to expand, the importance of warpage control has increased substantially.
The effective coefficient of thermal expansion (CTE) was reduced by 19%. Glass material's CTE is closer to that of silicon chips, resulting in less stress during temperature changes, which helps reduce cracks and solder joint fatigue.
The effective modulus of elasticity increased by 31%. A stiffer substrate is crucial for supporting large packages with increasing HBM stack layers.
In terms of power integrity, resistance decreased by 27% and inductance decreased by 42%, leading to a significant improvement in power delivery efficiency.
TSMC specifically emphasized that "no severe warpage and delamination/peeling" occurred during testing—these two issues have historically been major yield killers for large-scale packaging.
A Direct Challenge: Thinner Yet Superior
In this verification, TSMC provided a direct qualitative comparison between the two substrate types: Glass-SBT achieves "thin but better COP," while Organic-SBT is "thick but worse COP."
In other words, glass substrates can be made thinner while offering superior package flatness and reliability. This finding holds direct significance for the AI chip market, which pursues high-density, large-size packaging.
However, TSMC also clearly stated that further research is needed on glass thickness optimization and large CoWoS package layouts, indicating that full-scale mass production is still some distance away.
The Core Challenge: Through-Glass Vias
The core technical difficulty with glass substrates lies in Through Glass Via (TGV) technology.
Glass is inherently an insulator. Establishing tens of thousands of TGVs to create vertical conductive pathways is essential for signal and power transmission. However, glass also has high hardness and brittleness, making it prone to micro-cracks during processing, which affects reliability and yield.
Via formation, copper filling quality, and long-term thermal reliability are considered the three core hurdles for glass substrates to overcome on the path to mass production.
Supply Chain Dynamics: The Roles of Ibiden and Innolux
The list of collaborators itself reveals strategic supply chain positioning.
Ibiden is a key substrate supplier for NVIDIA and AMD AI chips and had previously announced a 500 billion yen investment to expand its new factory in Gifu Prefecture, focusing on high-end packaging substrates for AI servers. Its inclusion in TSMC's glass substrate verification collaboration further solidifies its core position in the next-generation packaging supply chain.
Innolux's involvement is seen by the industry as a significant step for a panel maker entering the glass substrate field. Panel manufacturers possess existing capabilities in large-format glass processing, and the collaboration with TSMC may open new business avenues for them.
Competitive Pressure from Intel and Samsung
TSMC's acceleration is driven by clear competitive pressure.
Intel has been developing glass substrate technology for over a decade, making it one of the earliest and most deeply invested players globally. Its glass substrate pilot production line in Arizona is gradually moving towards commercialization, aiming to combine glass substrates with ultra-large chiplet packaging to win orders for AI GPU and ASIC customers.
Samsung Electro-Mechanics (Semco) is establishing a glass substrate pilot production line in 2025 and has formed a joint venture with Japan's Sumitomo Chemical Group to build a glass substrate supply chain in advance.
In contrast, this marks TSMC's first public disclosure of glass substrate verification results. From a timeline perspective, TSMC's public move comes later than those of Intel and Samsung. However, its three-party verification path with Ibiden and Innolux, and its technical integration approach directly linking to the CoWoS/CoPoS packaging platforms, demonstrate that it is advancing rapidly according to its own strategic rhythm.
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