As the expansion of computing power in AI data centers drives Co-Packaged Optics (CPO) toward mass production, a previously overlooked aspect is emerging as a critical bottleneck for the entire supply chain: testing.
With AI data centers continuing to scale, traditional copper interconnects are approaching their physical limits. CPO is widely regarded by the industry as a key interconnect solution for next-generation AI infrastructure. Taiwan Semiconductor Manufacturing's COUPE platform is expected to enter mass production in 2026, marking CPO's transition from the laboratory to commercialization.
However, the inspection and testing phases for CPO remain significant hurdles. The industry currently lacks unified standards, and the processes are highly reliant on manual intervention, making testing a primary bottleneck constraining the large-scale mass production of CPO chips. A recent study by TrendForce provides a systematic analysis of this challenge.
Why is CPO testing so difficult? Understanding this requires first understanding the structure of CPO. CPO integrates optical components into a Photonic Integrated Circuit (PIC), which is then co-packaged with an Electronic Integrated Circuit (EIC) within a single chip. This approach uses optical paths to replace electrical ones, thereby reducing power consumption and latency. The bonded PIC and EIC component is referred to as an Optical Engine (OE).
Traditional EIC testing involves purely electrical measurements. In contrast, a PIC contains numerous optical components such as couplers, modulators, photodetectors, optical filters, and optical waveguides. Testing an OE requires specialized capabilities in three areas simultaneously: electrical, optical, and optoelectrical interaction, resulting in complexity far exceeding that of traditional chip testing.
PIC testing requires measuring parameters like Insertion Loss (IL), Polarization Dependent Loss (PDL), responsivity, waveguide propagation loss, and optical crosstalk. Currently, there are no unified testing standards for these parameters.
There is also a specific physical challenge: the precise alignment of optical probes. The process of coupling external light from an optical fiber into the OE's optical waveguide is called optical coupling. The core cross-sectional area of a single-mode fiber is approximately 78.5 square micrometers, whereas a typical optical waveguide cross-section is only about 0.099 square micrometers—a difference of nearly 800 times. Without nanometer-level alignment accuracy, coupling losses can be extremely high.
This means a fiber array must maintain an exact distance from the wafer or chip surface while fine-tuning the coupler angle to maximize optical power transmission, followed by scanning across different wavelength ranges. This set of operations still relies heavily on manual execution.
The result: 100% inspection of a single PIC chip can take over 100 seconds on average. This is one of the core obstacles to mass production of CPO chips.
Which is the most critical of the four testing stages? A CPO chip undergoes four testing stages from wafer to system: Stage 1: PIC Wafer Acceptance Test (WAT) – DC electrical and basic optical tests, including measurements of fundamental optical parameters like optical power, loss, and dark current. Stage 2: EIC-PIC Wafer-Level Test – Modulation functionality testing (electro-optical, opto-electrical, optical-optical), high-speed testing, and S-parameter measurement. Stage 3: OE-Level Test – Full calibration, DC testing, high-speed testing, optical loopback testing, and S-parameter measurement. This is the critical stage for confirming a "Known Good Optical Engine" (KGOE). Stage 4: Advanced Packaging Module-Level Test – Full system functional verification and optical loopback testing.
Among these four stages, the first one, PIC Wafer-Level Testing, is the most critical. The logic is straightforward: PICs are typically manufactured using mature process nodes, while EICs use more advanced, costly nodes. Identifying defective PICs at the wafer stage, before bonding them to expensive EICs, can prevent waste and significantly reduce losses in subsequent processing steps. This is similar to quality control on an assembly line – the earlier a problem is found, the smaller the loss.
Equipment Vendor Landscape: Giants Catching Up, New Players Entering The CPO test equipment market is rapidly taking shape, with integration between traditional Automatic Test Equipment (ATE) giants and specialized optical test vendors being a dominant trend.
Advantest and FormFactor The traditional EIC test market is dominated by Japan's Advantest and the US's Teradyne. CPO testing requires capabilities in both EIC and PIC testing, prompting both giants to partner with specialized optical probe vendors to fill the gap.
Advantest's approach involves collaboration with FormFactor. In June 2024, Advantest, alongside Jenoptik and Ayar Labs, introduced the UFO probe card, integrating electrical and optical probes on a single card to enable simultaneous electro-optical testing. A core innovation is alignment tolerance compensation technology—by specially shaping the output beam from the optical probe, optical signals can still enter the PIC coupler even with minor probe positioning errors, significantly reducing alignment time.
In April 2025, Advantest and FormFactor further launched the V93000-Triton photonic test system, equipped with 9-axis photonic alignment capability and FormFactor's OptoVue Pro optical alignment system. Its CalVue technology uses uniquely designed retroreflectors to observe the fiber array, combined with automated machine vision algorithms to calibrate Z-axis displacement and optical positioning in real-time, further compressing fiber alignment time.
Teradyne and ficonTEC Teradyne is pursuing a dual strategy of acquisition and partnership. In 2025, Teradyne acquired Quantifi Photonics and partnered with Germany's ficonTEC (now a subsidiary of China's Robo Technik).
In March 2025, the partners jointly launched the industry's first high-volume 300mm dual-side wafer probe test system. ficonTEC provided the WLT-D2 dual-side wafer test platform, featuring precise alignment capability within a 50nm range, enabling simultaneous electrical testing on the wafer top-side and optical testing on the bottom-side, thereby improving test efficiency. Teradyne contributed the UltraFLEXplus ATE and IG-XL system software.
Subsequently launched, the DLT-D1 is a dual-side die-level test system capable of connecting up to three parallel test heads simultaneously, increasing throughput and lowering test costs. With this, ficonTEC established a complete CPO test product line spanning from wafer-level to die-level.
Keysight Keysight, a global leader in measurement instruments, also offers a complete PIC wafer test solution, integrated with FormFactor and compatible with FormFactor's Velox probe control software.
Keysight's N778x series polarization controller can rapidly switch between different States of Polarization (SOP). Paired with the N7700100C Polarization Lambda Scan software, it uses a matrix method to derive parameters like IL, PDL, and TE/TM IL. This solution eliminates the need for polarization-maintaining fiber and manual pre-calibration of polarization at multiple wavelength points, significantly boosting test efficiency. Its SOP stabilization technology can also lock the input light's polarization state at a specific point, ensuring optical coupling stability throughout the wavelength scan.
Chroma Chroma is a global leader in System Level Test (SLT) equipment. Its Photodiode Aging & Reliability Test System series (Model 58604/58604-C/58606) is designed for reliability testing of PIC components like 3D sensors, lasers, photodetectors, and modulators. The Model 58606 provides 256 SMU channels per module layer and can be configured with up to 7 layers, totaling 1792 channels. Chroma has announced its intention to leverage its optical testing expertise from the SLT phase to invest in CPO test equipment development.
Enlitech In September 2025, Enlitech, in collaboration with iST, launched the Night Jar silicon photonics chip test platform. This is an add-on hyperspectral imaging analysis system that can be directly installed on probe stations from any brand, applicable across WAT, CP, and FT test stages.
Night Jar addresses a persistent industry pain point: previously, the location of light leakage within a waveguide could only be roughly estimated via reflected light, yielding only overall or average optical loss values. Night Jar can precisely locate light leakage points and measure the quantified IL value for specific waveguide segments or optical components, supporting wafer-level optical loss mapping. This helps R&D personnel identify defects more quickly and accurately, ultimately improving production yield.
Market Opportunity Window Opening As chip designs grow increasingly complex and SoC test difficulty rises, the number of test stations required per chip and the total test time are increasing. Consequently, the proportion of test equipment within semiconductor capital expenditure is rising. With CPO chips being incorporated into product portfolios, this share is expected to climb further.
The CPO test equipment market is forming. From an equipment vendor perspective, traditional ATE giants Advantest and Teradyne are rapidly building optical capabilities through M&A and partnerships, while players like Keysight, Chroma, and Enlitech are securing their positions in respective niches. The entire supply chain, from optical probes and metrology instruments to automatic test equipment, is reorganizing around the demands of CPO testing.
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