Recently, NVIDIA officially launched its next-generation Spectrum-6 Ethernet switch chip, designed to support hyperscale AI infrastructure based on the Vera Rubin platform.
NVIDIA stated that the Spectrum-6 switch chip will serve as the core component of the next-generation Spectrum-X Ethernet switch platform. It aims to enhance the overall computational efficiency of AI factories through high bandwidth, intelligent traffic management, and fault recovery capabilities. AI infrastructure builders, including CoreWeave, Microsoft, Nebius, SpaceXAI, and Tesla, will be among the first to adopt Spectrum-6 to accelerate the construction of their AI factories.
In terms of product performance, Spectrum-6 offers a single-switch capacity of 102.4 Tbps, double that of the previous generation. It is designed to connect hundreds of thousands of GPUs and CPUs, providing network support for large-scale AI training, agent applications, and inference tasks. Based on this, the Spectrum-X Ethernet switch can achieve AI network performance 1.6 times higher than standard Ethernet and maintain network efficiency of up to 95% in deployments exceeding 100,000 GPUs.
Furthermore, the Spectrum-6 switch chip supports both pluggable optical modules and co-packaged optics (CPO), as well as liquid cooling. This provides a comprehensive end-to-end cooling solution for entire AI factories while improving network power efficiency.
As of now, switches based on Spectrum-6 have entered full production and are being deployed in gigawatt-scale AI factories worldwide.
China Galaxy pointed out that Spectrum-X Ethernet Photonics is the world's first CPO switch with 200G/lane capabilities to enter mass production. The mass production of Vera Rubin's Spectrum-X Ethernet Photonics further validates the value of optical interconnects in next-generation AI data centers. The increasing penetration of silicon photonics technology is also expected to drive rapid growth in demand for upstream optical chips.
▌Switches Become Token Generation Multipliers
A switch is a network device used for Dian Guang signal forwarding. In NVIDIA's view, AI performance is fundamentally a networking problem.
The company noted that the world's most advanced AI factories aggregate hundreds of thousands of GPUs and CPUs to train cutting-edge models, power agent AI, and generate intelligence at an unprecedented scale. At this level, the network becomes a key computational multiplier driving token generation.
Focusing on the switch domain has also brought this tech giant customer and revenue growth.
As one of the first users of the Spectrum-6 switch chip, CoreWeave stated: "Introducing NVIDIA Spectrum-6 and liquid-cooled Spectrum-X Ethernet infrastructure into our AI factories helps us provide our customers with the bandwidth, resilience, and efficiency needed to train cutting-edge models and deploy inference faster."
According to the latest IDC data, NVIDIA became the revenue leader in the global data center Ethernet switch market for the first time in Q1 FY2026. In the past, this field was dominated by networking giants like Broadcom and Cisco.
Kaiyuan Securities noted that from the perspective of the switch chip to GPU ratio, the traditional architecture has a ratio of approximately 3 switches to 64 GPUs. In contrast, NVIDIA's NVL72 contains 72 GPUs and 9 switch trays. Each GBNVL72 switch tray is equipped with 2 switch chips, resulting in a switch chip to GPU ratio of 1:4. The latest VRNVL72 switch tray doubles the number of switch chips, further improving the ratio to 1:2. As Scale-out and Scale-up architectures evolve in parallel, the weight of the switching network within computing clusters may gradually increase.
The institution emphasized that the switching network is transitioning from a supporting role in computing power infrastructure to a core protagonist in clusters. As AI model parameters expand, the demand for computing power has shifted from simple GPU stacking to a comprehensive reconstruction of the system architecture. Constrained by the physical power density of single chips, interconnect bandwidth, and memory capacity bottlenecks, the marginal benefits of increasing computing power continue to diminish. The switching network has become the ceiling limiting computing power. Currently, system-level collaborative architectures (such as high-bandwidth domain interconnects) are the main technical path to break through single-chip performance limits.
(Source: Cailian Press)
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