Samsung Electronics has achieved consecutive milestones along its AI memory technology roadmap. Following its lead in mass-producing the sixth-generation high-bandwidth memory HBM4, the company is now reporting positive progress on both the seventh-generation HBM4E and the next-generation DRAM process, solidifying the groundwork for its technological leadership in the upcoming round of AI memory competition.
According to industry sources, Samsung's Chief Technology Officer and Head of the Semiconductor Research Institute, Song Jae-hyuk, stated during an internal business briefing for the Device Solutions (DS) division on June 30th that the reliability test yield for HBM4E has surpassed 70%. The industry typically regards an 80% yield as the threshold for a "mature and stable" process. While HBM4E is still in the reliability testing phase, a yield above 70% is seen as a clear indicator that the development process has officially entered a stable phase.
Simultaneously, Song Jae-hyuk revealed at the same event that the next-generation 10nm-class 7th-generation DRAM process (D1d) has gained a competitive edge over rivals in terms of technological competitiveness. The company plans to complete its Production Readiness Approval (PRA) for this process in November of this year.
The combination of these two advancements has led the market to hold a more optimistic outlook for Samsung's competitive prospects in the next-generation AI memory arena.
HBM4E Development Accelerates with Smooth Sample Evaluation
Samsung was first to achieve mass production and shipment of HBM4 in February this year. On May 29th, it further disclosed detailed technical specifications for its 12-layer HBM4E product and began sending samples to key customers. HBM4 is set to be featured in Nvidia's AI accelerator "Vera Rubin," scheduled for release in the second half of this year. HBM4E, as its successor, is planned for integration into Nvidia's next-generation AI accelerator "Vera Rubin Ultra" and other products launching next year.
Industry insiders note that as sample evaluations by major customers progress steadily, the mass production development work for HBM4E is proceeding smoothly in parallel. Against this backdrop, the rise in reliability test yield above 70% holds significant importance. Although this figure has not yet reached the industry's recognized standard for mature yield, considering the current development stage of the product, it is widely interpreted as a positive signal that HBM4E is rapidly converging towards meeting mass production conditions.
D1d Process Advances with Target for November Mass Production Approval
Regarding the development of the next-generation DRAM process, Song Jae-hyuk stated that the D1d process has already achieved technological leadership over competitors. The development target is to obtain Production Readiness Approval (PRA) in November. PRA is the final internal quality assessment procedure before product shipment, comprehensively verifying yield, performance, and production efficiency to determine readiness for mass production. Passing this approval allows for the official transition to a mass production system.
The strategic significance of the D1d process extends beyond DRAM itself. Samsung plans to fully adopt this process starting from the eighth-generation HBM5. The industry believes that if the D1d development proceeds as planned, it will have a cascading positive effect on the overall competitiveness of next-generation DRAM and subsequent HBM5 products.
Internal Tensions Emerge Over R&D Compensation
While technological progress was announced, another layer of discussion emerged within Samsung's DS division. Following this briefing, discontent within the R&D organization regarding role recognition and compensation structure reportedly intensified, with some members calling for the company to more actively acknowledge the contributions of the R&D organization.
Management and labor at Samsung had previously reached an agreement for the DS division to establish a "Special Business Performance Bonus" system, funded by 10.5% of the division's operating profit. However, within the DS division, there is a significant disparity in performance bonuses between the memory business and public sectors (including the research institute), as well as the non-memory business (System LSI and foundry). Calls to improve the compensation structure are growing louder.
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