NVIDIA is undertaking a significant overhaul of the memory architecture for its next-generation AI accelerator platform, involving two parallel tracks: a downgrade in stacking specifications and a downward revision of bandwidth metrics, reflecting deeper supply chain pressures and cost optimization logic in the high-bandwidth memory sector.
According to ZDNet, Samsung and SK Hynix are preparing to supply 8-high HBM4 to NVIDIA's Rubin Ultra in the second quarter of 2027, a move that suggests the originally planned 12-high HBM4E approach may be altered. Meanwhile, according to Wccftech, NVIDIA quietly reduced the HBM4 bandwidth specifications for the Vera Rubin platform as early as September last year 鈥?bandwidth per Rubin GPU was cut by approximately 13%, while the HGX Rubin NVL8 system-level reduction reached as high as 26%.
These adjustments have direct implications for HBM suppliers and the broader GPU supply chain. A lower bandwidth threshold means more HBM4 products are likely to pass NVIDIA's qualification process, potentially expanding the pool of suppliers; and the introduction of 8-high configurations will reduce the cost and bill-of-materials burden per HBM stack, which is expected to ease capacity bottlenecks amid persistently tight HBM supply.
Rubin Ultra Abandons 12-High Plan, Pivots to 8-High HBM4 Mix
According to ZDNet, 8-high HBM4 was not originally part of NVIDIA's plans, but as the company re-examined the memory configuration for Rubin Ultra, related discussions gained momentum in the third quarter of 2026. The report noted that Rubin Ultra was originally intended to rely on 12-high HBM4E, but the final product may instead adopt a mixed solution of 8-high HBM4 and HBM4E to alleviate supply constraints caused by thermal management challenges and low yields associated with 12-high stacking.
ZDNet, citing people familiar with the matter, reported that NVIDIA is expected to deploy both 8-high HBM4 and 8-high HBM4E in Rubin Ultra-based NVL rack-scale systems, depending on rack configurations. Notably, while both Samsung and SK Hynix have completed NVIDIA's qualification for 12-high HBM4, their 8-high products still need to pass a separate certification process.
TrendForce analysis pointed out that compared with 12-high HBM modules, 8-high configurations use fewer DRAM chips, which can simultaneously reduce the cost per stack and the overall GPU bill-of-materials cost, and can support more GPUs with the same HBM bit output. Given persistently tight HBM supply, the 8-high approach is expected to become a priority evaluation option for many GPU and ASIC manufacturers in 2027.
The ZDNet report also indicated that while 12-high HBM4 remains the mainstream configuration in 2026, adoption of 8-high HBM4 is expected to rise sharply from mid-2027. This trend may extend beyond NVIDIA 鈥?Economy Tribune, citing Daishin Securities analysis, reported that Anthropic's in-house AI chip may also adopt 8-high HBM4, with Samsung potentially handling both foundry and memory supply for the project.
Bandwidth Metrics Quietly Revised Down, Qualified Supplier Pool Set to Expand
On the bandwidth specification adjustments, according to Wccftech, an archived version of NVIDIA's official specifications page dated September 1 showed the Vera Rubin NVL72 system equipped with 20.7 TB of HBM4 capacity and 1,580 TB/s of bandwidth, the Vera Rubin superchip featuring 576 GB per die with 44 TB/s of bandwidth, and each Rubin GPU corresponding to 288 GB and 22 TB/s.
NVIDIA subsequently quietly lowered the specifications: HBM4 bandwidth per GPU dropped from 22 TB/s to 19.2 TB/s, while NVLink 6 throughput fell from 3.6 TB/s to 3 TB/s, representing reductions of approximately 13% and 17% respectively. According to IT Home, the Vera CPU's memory specification was also adjusted from a fixed 1.5 TB of LPDDR5X per chip to "up to 1.5 TB."
Economy Tribune noted that all three major memory manufacturers have now disclosed HBM4 performance data: Samsung and SK Hynix's HBM4 offers a data transfer rate of 11.7 Gbps per pin (Samsung up to 13 Gbps), while Micron exceeds 11 Gbps, corresponding to per-stack HBM4 bandwidth of approximately 3.0 TB/s (Samsung, SK Hynix) and over 2.8 TB/s (Micron) respectively.
Calculating based on eight 36 GB HBM4 stacks integrated per Rubin GPU, achieving the original 22 TB/s bandwidth would require approximately 10.7 Gbps per pin, while the revised 19.2 TB/s target corresponds to a pin rate of about 9.4 Gbps. Economy Tribune analysis suggested that, theoretically, the performance data disclosed by memory manufacturers is sufficient to meet NVIDIA's original targets; IT Home further pointed out that after lowering bandwidth requirements, more HBM4 products are expected to obtain Rubin GPU qualification, and overall output is likely to increase accordingly.
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