Semiconductor Testing: AI's Next Growth Bottleneck

Over the past two years, AI hardware investment has focused mainly on GPUs, HBM, and advanced packaging. But as chips become more powerful and structurally complex, another part of the supply chain is becoming increasingly important: semiconductor testing.

Nomura believes AI chip upgrades are steadily increasing the value of back-end manufacturing. Longer test times, tighter capacity, outsourced orders, and higher equipment requirements are improving the strategic position of testing suppliers.

The core investment logic is simple: even if AI chip shipment growth slows, testing content per chip can continue to rise.

Why Testing Matters More in the AI Era

AI chips cannot be shipped immediately after production. They must pass wafer probing, final testing, burn-in, and system-level testing to confirm that they can operate reliably under high power, high temperatures, and real server workloads.

The more complex the chip, the more functions must be validated—and the longer the test process becomes.

From Hopper to Rubin: Testing Time Keeps Rising

Using NVIDIA's AI GPUs as an example, Nomura estimates that if Hopper's final-test time is set at 1:

– Blackwell could require around 4 times as long

– Rubin could require around 7 times as long

System-level and burn-in testing are also expected to increase.

Testing costs as a share of total manufacturing costs could rise from approximately 1.9% for Hopper to 2.5% for Blackwell and 3.3% for Rubin.

This means product upgrades alone can increase demand for testers, handlers, probe cards, sockets, and thermal-control equipment.

Advanced Packaging Creates a "Yield Cliff"

Advanced AI accelerators combine GPUs, HBM, I/O dies, and other components in a single package.

The more dies included, the greater the risk that one defective component makes the entire package unusable. If each die has a 90% yield, combining ten dies would produce a theoretical module yield of only about 35%.

That makes early testing critical.

Manufacturers must identify Known Good Dies before they enter expensive packaging processes. Testing therefore moves earlier in production and requires more advanced wafer probing, probe cards, sockets, and test interfaces.

As Chiplets, CoWoS, SoIC, 2.5D packaging, and hybrid bonding expand, testing becomes a larger part of the total manufacturing value chain.

CPO Could Create a New Testing Market

Co-packaged optics, or CPO, adds another layer of complexity.

Traditional chip testing focuses mainly on electrical signals. CPO combines electronic and photonic chips, requiring manufacturers to test:

– Electrical performance

– Optical performance

– Communication between the two

A single CPO product may require several testing stages, from separate wafer testing to hybrid-bond testing, optical-engine validation, and final module testing.

If CPO moves into volume production, it could create new demand for automatic test equipment, probe cards, optical instruments, sockets, and temperature-control systems.

Which Parts of the Value Chain Could Benefit?

The main beneficiaries fall into four groups.

1.Test Equipment and Thermal Handling

Automatic test equipment acts as the “brain” of the testing system, sending electrical signals into the chip and evaluating whether it performs correctly.

$Teradyne(TER)$   is the most important U.S.-listed ATE company. Longer AI-chip test times should directly increase demand for its equipment. In CPO, the company may also participate in the electrical side of module-level testing.

$Cohu(COHU)$   offers testers, handlers, sockets, burn-in boards, and thermal-control equipment. Its AI exposure is less concentrated than Teradyne’s, but it can still benefit from broader testing-market growth.

$inTest(INTT)$   focuses on thermal-management equipment and wafer chucks. As AI-chip power density rises, precise temperature control becomes increasingly important during both wafer and final testing.

2.Probe Cards and Test Interfaces

Probe cards help identify defective dies before packaging, making them essential in advanced packaging.

$FormFactor (FORM.US)$ is one of the largest global probe-card suppliers and one of the clearest U.S.-listed beneficiaries of the Known Good Die trend.

Its customer base spans both logic and memory chips, while its growing exposure to NVIDIA and other advanced-chip customers gives it direct AI relevance.

FormFactor is also developing CPO wafer-testing systems, giving it exposure to both probe-card upgrades and a new optical-testing market. 

3.Packaging and Testing Services

As test requirements increase and orders move from foundries to specialist providers, outsourced semiconductor assembly and testing companies may capture more value.

$Amkor Technology (AMKR.US)$ is one of the most direct U.S.-listed OSAT names, with exposure to 2.5D packaging, fan-out, wafer-level packaging, and final testing.

$ASE Technology (ASX.US)$ is another global packaging and testing leader. It stands to benefit from higher AI packaging content, more complex testing, and order spillover from foundries.

These companies benefit twice: first from packaging-capacity expansion, and second from the rising testing value attached to each advanced chip.

4.Optical and High-Speed Test Instruments

CPO also creates opportunities for companies that measure optical and high-frequency signals.

$Keysight Technologies (KEYS.US)$ is a leader in RF, high-speed, and semiconductor measurement. As CPO adoption expands, demand could increase for optical, signal-integrity, and protocol-testing equipment.

$Viavi Solutions (VIAV.US)$ also offers exposure to optical-network and photonics testing, although its earnings sensitivity to CPO remains less visible.

$Emerson Electric (EMR.US)$ participates through National Instruments, while Ralliant (RAL) provides oscilloscopes and mixed-signal testing through Tektronix. Both are broader industrial names rather than pure semiconductor-testing plays.

Investment Takeaway

The semiconductor-testing opportunity is not based only on higher chip volumes.

It is driven by three structural changes:

1. Each AI chip requires more testing time

2. Advanced packaging adds more test steps

3. CPO introduces an entirely new optical-testing layer

The key risk is that demand still depends on hyperscaler capital spending, AI-chip launches, advanced-packaging expansion, and the pace of CPO commercialization.

Bottom Line

For most of the AI cycle, investors have focused on who can manufacture the most powerful chips.

The next phase may increasingly reward the companies that can prove those chips work reliably before they are deployed.

As AI chips become more expensive and complex, testing must happen earlier, last longer, and use more advanced equipment. That is why semiconductor testing is moving from a supporting process to a critical part of the AI hardware supply chain.

@TigerStars  @CaptainTiger  @TigerWire  @Daily_Discussion  @Tiger_chat  @Tiger_comments  @MillionaireTiger