Constraints on the supply side of artificial intelligence computing infrastructure are expanding comprehensively from front-end chip manufacturing to optical components and advanced packaging materials. A Broadcom executive has, for the first time, identified three major bottlenecks in the AI supply chain, revealing that the true chokepoints in this computing arms race are far more profound than widely understood by the market and are difficult to resolve in the short term.
At a media briefing in Taipei on March 24, Natarajan Ramachandran, Director of Physical Layer Product Marketing at Broadcom, pointed out that the AI-related supply chain currently faces three core bottlenecks: laser production capacity, wafers (specifically referring to Taiwan Semiconductor Manufacturing's advanced processes), and PCBs (Paddle Cards). Among these, the lead time for the small PCBs used inside high-speed optical transceivers has surged from approximately six weeks to about six months, with relief not expected until 2027.
The direct implication of these remarks for the market is that the investment boom in AI infrastructure cannot automatically resolve these structural supply-side constraints. From laser yields falling below 30% under stringent testing, to low initial unit output from Taiwan Semiconductor Manufacturing's advanced packaging, and PCB supplier qualification cycles lasting over six months—the compounding effect of multiple bottlenecks suggests that the computing capacity gap is likely to persist structurally, and supply chain price increases may become normalized.
Broadcom CEO Hock Tan also confirmed during the March earnings call that the company has proactively secured supplies of key components for 2026 through 2028, covering advanced process wafers, high-bandwidth memory (HBM), and substrates. This forward-looking strategy itself is a direct reflection of the current severity of supply constraints.
**PCB Lead Times Surge Tenfold** In high-end 800G/1.6T optical transceiver modules, the PCB serves as the critical interface connecting external cables to internal optoelectronic components. These small PCBs, due to extremely limited space and the need to handle very high-frequency signals, typically use mSAP (modified semi-additive process) technology, which has a much higher technical barrier than standard PCBs and is primarily supplied by manufacturers with advanced HDI or IC substrate capabilities.
The root cause of the PCB bottleneck lies in process overlap. The mSAP manufacturing process shares some commonalities with the IC substrate processes required for AI servers. As global demand for HBM capacity intensifies, capacity for these small PCBs is consequently squeezed. Furthermore, 1.6T modules impose extremely stringent signal quality requirements, necessitating the use of ultra-low-loss materials and precise impedance control on the PCBs, capabilities beyond the reach of most standard PCB manufacturers.
Critically, once a supplier is changed, the qualification cycle can extend beyond six months. This is precisely why hyperscale cloud providers like Google and Meta prefer to sign three-to-four-year long-term contracts to lock in capacity from their existing suppliers.
**Lasers: Sub-30% Yield, Indium Phosphide Capacity Emerges as Core Chokepoint** Laser components have become another significant bottleneck in the era of CPO (co-packaged optics). To support 1.6T and even higher bandwidths, lasers must maintain wavelength stability in high-temperature data center environments, imposing strict requirements for "ultra-high power" and "extremely low noise" continuous wave (CW) lasers. Even if suppliers can produce laser dies, after rigorous reliability testing, the yield rate meeting the high standards for CPO applications may be less than 30%.
Capacity constraints are equally severe. High-power lasers rely on Indium Phosphide (InP) technology, and there are very few manufacturers globally with mass production capability for 6-inch InP wafers. If upstream InP epitaxial wafer suppliers or vertically integrated companies like Coherent and Lumentum are operating at full capacity, downstream packaging houses will have no laser dies available, regardless of their number.
A deeper structural pressure stems from the amplifying effect of the CPO architecture itself on laser demand. In traditional optical modules, one laser is configured per module. In CPO solutions, to mitigate thermal impacts, the industry is shifting towards ELSFP (external light source module) architectures. This disrupts the linear relationship between laser die demand and switch count, instead creating a multiplicative increase, directly impacting the already strained InP epitaxial wafer capacity.
**Wafers and Advanced Packaging: The Real "Super Traffic Jam" is in Back-End** Regarding wafer supply, Natarajan Ramachandran directly stated that "Taiwan Semiconductor Manufacturing's capacity is maxed out," anticipating that its advanced process production lines will become a bottleneck in 2026, even though the company plans continuous expansion through 2027.
However, the real "super traffic jam" is occurring in the back-end advanced packaging phase. Entering the CPO era, Taiwan Semiconductor Manufacturing must adopt COUPE (compact universal photonic engine) technology, which involves 3D stacking of optical chips and silicon chips using hybrid bonding. This entirely new packaging technology is extremely challenging, with very long testing cycles, resulting in difficulty in rapidly increasing initial unit per hour (UPH) output from equipment.
The competitive landscape further intensifies capacity pressure. By 2026, Broadcom's competitors for capacity will no longer be just traditional networking and communications companies, but also Nvidia, Apple, AMD, Qualcomm, and giants like Google, Meta, and OpenAI, which are heavily investing in developing their own ASIC chips. When the most advanced AI computing chips and the highest-end 1.6T network switches simultaneously converge on the same Taiwan Semiconductor Manufacturing production lines, capacity effectively enters a "rationing" system.
Even if Taiwan Semiconductor Manufacturing decided now to massively expand production, the lead times for factory construction, cleanroom completion, and delivery of equipment like ASML's extreme ultraviolet (EUV) lithography tools and various high-end testing apparatus often range from twelve to eighteen months. This means that 2026 capacity is essentially being locked in by major players during 2024 and 2025—clients placing orders now may have to wait until new capacity comes online in 2027.
**Chain-Wide Spillover: Secondary Supplier Expansion Lags, Bottlenecks Spread** Capacity pressure is spilling over across the entire supply chain. Advanced packaging is not solely the concern of packaging houses; the real potential chokepoints include: the ABF substrates required for CoWoS, underfill materials essential for advanced packaging, thermal dissipation demands driven by exploding AI power consumption, known-good-die (KGD) testing and burn-in processes, CPO and optical modules, and processes like TSV and interposer dicing and drilling.
Taiwan Semiconductor Manufacturing Chairman C.C. Wei has previously stated that "CoWoS capacity is still insufficient"—the shortfall is not capital, but rather the capacity of supporting suppliers: substrate manufacturers, probe card makers, underfill suppliers, etc. Taiwan Semiconductor Manufacturing can invest heavily in building factories, but it cannot force these small and medium-sized suppliers to double their capacity in the short term. Expanding ABF substrate production typically takes two to three years, burn-in testing times are lengthy, and fiber array alignment tolerances are sub-micron, making full automation difficult—each link in the chain is slowing the overall pace.
As Nvidia continues to advance hardware iterations of its GPU architecture, supply chain bottlenecks and pricing issues are likely to become structural norms rather than cyclical disruptions. For investors, the locations of these capacity chokepoints are precisely where pricing power is concentrated.
